PN-Junction Temperature Sensing Apparatus

• US 20070158776A1
• Filed: 12/04/2006
• Published: 07/12/2007
• Est. Priority Date: 06/04/2004
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Cardoso, Andre, Chatinho, Vitor, Monteiro, Antonio, Julio, Alexandre
• Granted Patent: US 7,758,240 B2
• Time in Patent Office: Days
• US Class Current: 257/486
• CPC Class Codes: G01K 7/01 using semiconducting elements having PN junctions G01K7/02, G01K7/16, G01K7/30 take precedence

Abstract

A PN-junction temperature sensing apparatus for applying input signals to a semiconductor device and measuring temperature-dependent output signals has an odd number of current sources (1, 2, n) switches (5, 6, 7) with selectable outputs to connect the current sources (5, 6, 7) with a thermal sensor (12) or a sink diode (13) and an A/D converter (17) to digitize the measured voltage of the thermal sensor (12). A digital processor (18) controls the switches (5, 6, 7) and stores the digitized voltage values in a memory. Provided algorithms allow the usage of these values to provide a calibrated measurement of temperature and also sensor life estimation.

Claims

1. A PN-junction temperature sensing apparatus comprising:

a band gap based current reference, which is mirrored in 3 or higher odd number of usable 1;

1 current sources wherein each mirrored current source comprise a p-type MOSFET transistor being source connected to V_DD;

switches having two selectable outputs controlled by a digital processor, wherein each switch is connected with the drain of each current source and wherein a first output of each switch is connected to an anode of a PN-junction thermal sensor and a second output of each switch is connected to an anode of a sink diode and wherein the cathodes of both components are connected to a common level;

an integrated A/D converter to digitize the voltage across the PN-junction sensor, wherein the value of the digitized voltage is stored in a memory of the digital processor.

2. The apparatus according to claim 1, wherein the PN-junction thermal sensor is made of re-usable IC-scrap material.

3. The apparatus according to claim 1, wherein the sink diode is substituted by another PN-junction thermal sensor device.

4. The apparatus according to claim 1, wherein the source of current reference is connected to its gate.

5. The apparatus according to claim 1, wherein the current sources are arranged in two mirrored half parts.

6. The apparatus according to claim 1, wherein a memory of said digital processor is a non-volatile memory selected from the group consisting of EEPROM, Flash and NVRAM.

7. The apparatus according to claim 1, wherein a basic algorithm of the PN-junction temperature sensing apparatus is improved by adding a serial resistance factor (R_s) to said model, which requires at least one more energizing level (I₂) and is written as a system of two or more equations, wherein for n current levels, the n−

1 equation system is

Δ

V₁=T·

k/q·

ln(I₁/I₀)+Rs·

(I₁−

I₀₎
Δ

V₂=T·

k/q·

ln(I₂/I₀)+Rs·

(I₂−

I₀₎
. . .
Δ

V<sub>n−

1</sub>=T·

k/q·

ln(I<sub>n−

1</sub>/I₀)+Rs·

(I<sub>n−

1</sub>−

I₀₎

wherein I₀ is a constant reference current, which is in the range of nA or pA for a small signal Si diode at ambient temperature.

8. The apparatus according to claim 1, wherein the apparatus implements an improved method, which is sensitive to increasing serial resistance, resulting in the following equations 16 and 17:

Δ

V₁=T·

k/q·

ln(I₁/I₀)a₁(T)·

(1−

I/I₀)/(1+[I/I₀]ˆ

a₂(T))+Rs·

(I₁−

I₀) 

 

[16a]
Δ

V<sub>n−

1</sub>=T·

k/q·

ln(I<sub>n−

1</sub>/I₀)/(+a₁(T)·

(1−

I<sub>n−

1</sub>/I₀]ˆ

a₂(T))+Rs·

(I₁−

I₀) 

 

[16b]
or
Δ

V₁=T·

k/q·

ln(r₁)+a₁(T)·

(1−

r₁)/(1+[r₁]ˆ

a₂(T))+Rs·

(r₁−

1)·

I₀ 

 

[17a]
Δ

V<sub>n−

1</sub>=T·

k/q·

ln(r<sub>n−

1</sub>)+a₁(T)·

(1−

r<sub>n−

1</sub>)/(1+[r<sub>n−

1</sub>]ˆ

a₂(T))+Rs·

(r<sub>n−

1</sub>−

1)·

I₀,n≧

5 

 

[17b]

wherein a₁(T) and a₂(T) are parameters for the description of high current characteristic behaviour and I₀ is a constant reference current.

9. The apparatus according to claim 1, wherein the apparatus implements a serial resistance R_s of a proper PN-junction junction model, which takes into account the aging of the diode-based temperature sensor, in that the response of two equivalent PN-junctions of the same die but with divergent electrical usage are composed, wherein a record with the significant model parameters is kept for each diode sensor, and wherein this record dictates the “

end of life”

of the sensing PN-junction and at least the temperature and a model parameter history is kept in non-volatile memory selected from the group consisting of NVRAM, EEPROM and Flash, by increasing the recording rate for an increasing PN-junction behaviour drift.

10. The apparatus according to claim 1, wherein the apparatus implements an auto-calibration, wherein the ratio between two current source banks are using an internal resistor, in such a way that the maximum level for the lower energy bank and the lowest level for the higher energy bank can fit in an A/D converter range, wherein the resistor is selected from an internal bank of resistors, wherein the resistivity of said resistor is stable inside the adopted IC technology typical working temperature range and wherein the current density is not as high to heat the integrated thin-film resistor beyond that upper limit, preferably a polysilicon resistor in CMOS-technology is implemented.

11. A method of using the apparatus according to claim 1 for thermal image arrays to increase accuracy of same by using the apparatus to implement the lowest I/0 layout mathematically achievable.

12. A PN-junction temperature sensing apparatus comprising:

a band gap based current reference, which is mirrored in 3 or higher odd number of usable 1;

1 current sources wherein each mirrored current source comprise a p-type MOSFET transistor being source connected to V_DD;

switches having two selectable outputs controlled by a digital processor, wherein each switch is connected with the drain of each current source and wherein a first output of each switch is connected to an anode of a PN-junction thermal sensor and a second output of each switch is connected to an anode of another PN-junction thermal sensor device and wherein the cathodes of both components are connected to a common level;

an integrated A/D converter to digitize the voltage across the PN-junction sensor, wherein the value of the digitized voltage is stored in a memory of the digital processor.

13. The apparatus according to claim 12, wherein the PN-junction thermal sensor is made of re-usable IC-scrap material.

14. The apparatus according to claim 12, wherein the source of current reference is connected to its gate.

15. The apparatus according to claim 12, wherein the current sources are arranged in two mirrored half parts.

16. The apparatus according to claim 12, wherein a memory of said digital processor is a non-volatile memory selected from the group consisting of EEPROM, Flash and NVRAM.

17. The apparatus according to claim 12, wherein a basic algorithm of the PN-junction temperature sensing apparatus is improved by adding a serial resistance factor (R_s) to said model, which requires at least one more energizing level (I₂) and is written as a system of two or more equations, wherein for n current levels, the n−

1 equation system is

Δ

V₁=T·

k/q·

ln(I₁/I₀)+Rs·

(I₁−

I₀)
Δ

V₂=T·

k/q·

ln(I₂/I₀)+Rs·

(I₂−

I₀)
. . .
Δ

V<sub>n−

1</sub>=T·

k/q·

ln(I<sub>n−

1</sub>/I₀)+Rs·

(I<sub>n−

1</sub>−

I₀)

wherein I₀ is a constant reference current, which is in the range of nA or pA for a small signal Si diode at ambient temperature.

18. The apparatus according to claim 12, wherein the apparatus implements an improved method, which is sensitive to increasing serial resistance, resulting in the following equations 16 and 17:

Δ

V₁=T·

k/q·

ln(I₁/I₀)+a₁(T)·

(1−

I/I₀)/(1+[I/I₀]ˆ

a₂(T))+Rs·

(I₁−

I₀) 

 

[16a]
Δ

V<sub>n−

1</sub>=T·

k/q·

ln(I<sub>n−

1</sub>)/[I₀)+a₁(T)·

(1−

)/[I<sub>n−

1</sub>/I₀]ˆ

a₂(T))+Rs·

(I₁−

I₀) 

 

[16b]
or
Δ

V₁=T·

k/q·

ln(r₁)+a₁(T)·

(1−

r₁)/(1+[r₁]ˆ

a₂(T))+Rs·

(r₁−

1)·

I₀ 

 

[17a]
Δ

V<sub>n−

1</sub>=T·

k/q·

ln(r<sub>n−

1</sub>)+a₁(T)·

(1−

r<sub>n−

1</sub>)/(1+[r<sub>n−

1</sub>]ˆ

a₂(T))+Rs·

(r<sub>n−

1</sub>−

1)·

I₀, n≧

5 

 

[17b]

wherein a₁(T) and a₂(T) are parameters for the description of high current characteristic behaviour and I₀ is a constant reference current.

19. The apparatus according to claim 12, wherein the apparatus implements a serial resistance R_s, of a proper PN-junction junction model, which takes into account the aging of the diode-based temperature sensor, in that the response of two equivalent PN-junctions of the same die but with divergent electrical usage are composed, wherein a record with the significant model parameters is kept for each diode sensor, and wherein this record dictates the “

end of life”

of the sensing PN-junction and at least the temperature and a model parameter history is kept in non-volatile memory selected from the group consisting of NVRAM, EEPROM and Flash, by increasing the recording rate for an increasing PN-junction behaviour drift.

20. The apparatus according to claim 12, wherein the apparatus implements an auto-calibration, wherein the ratio between two current source banks are using an internal resistor, in such a way that the maximum level for the lower energy bank and the lowest level for the higher energy bank can fit in an A/D converter range, wherein the resistor is selected from an internal bank of resistors, wherein the resistivity of said resistor is stable inside the adopted IC technology typical working temperature range and wherein the current density is not as high to heat the integrated thin-film resistor beyond that upper limit, preferably a polysilicon resistor in CMOS-technology is implemented.