Heterogeneously integrated microsystem-on-a-chip

• US 20070158787A1
• Filed: 11/13/2003
• Published: 07/12/2007
• Est. Priority Date: 11/13/2003
• Status: Active Grant

• Current Assignee: National Technology & Engineering Solutions Of Sandia LLC (Honeywell International Inc.)
• Original Assignee: Sandia Corporation (Martin Marietta Corporation)
• Inventors: Chanchani, Rajen
• Granted Patent: US 7,335,972 B2
• Time in Patent Office: Days
• US Class Current: 257/619
• CPC Class Codes: B81C 1/00238 Joining a substrate with an electronic processing unit and a substrate with a micromechanical structure
• CPC Class Codes: B81C 2201/0191 Transfer of a layer from a carrier wafer to a device wafer
• CPC Class Codes: B81C 2203/058 Aligning components using methods not provided for in B81C2203/051 - B81C2203/052
• CPC Class Codes: B81C 3/002 Aligning microparts
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/6836 Wafer tapes, e.g. grinding or dicing support tapes adhesive tapes in general C09J7/20
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2221/68327 used during dicing or grinding
• CPC Class Codes: H01L 2221/6834 used to protect an active side of a device or wafer
• CPC Class Codes: H01L 2221/68363 used in a transfer process involving transfer directly from an origin substrate to a target substrate without use of an intermediate handle substrate
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 25/16 the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/09701 Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/16195 : Flat cap [not enclosing an internal cavity]
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/30107 : Inductance

Abstract

A microsystem-on-a-chip comprises a bottom wafer of normal thickness and a series of thinned wafers can be stacked on the bottom wafer, glued and electrically interconnected. The interconnection layer comprises a compliant dielectric material, an interconnect structure, and can include embedded passives. The stacked wafer technology provides a heterogeneously integrated, ultra-miniaturized, higher performing, robust and cost-effective microsystem package. The highly integrated microsystem package, comprising electronics, sensors, optics, and MEMS, can be miniaturized both in volume and footprint to the size of a bottle-cap or less.

Claims

1. A microsystem-on-a-chip, comprising:

a bottom chip comprising one or more microsystem devices with associated input/output pads on the top surface of the bottom chip;

an interconnect layer on the top surface of the bottom chip, the interconnect layer comprising a compliant dielectric material and an interconnect structure embedded in the compliant dielectric material, the interconnect structure comprising one or more via capture pads connected to the associated input/output pads on the top surface of the bottom chip; and

a thin upper chip on the interconnect layer, the thin upper chip comprising one or more microsystem devices with associated input/output pads on the top surface of the thin upper chip that are connected to the one or more via capture pads in the interconnect layer by conductive vias through the thin upper chip.

2. The microsystem-on-a-chip of claim 1, further comprising at least one additional stacked layer on the thin chip, each additional stacked layer comprising:

a stacked interconnect layer on the top surface of the thin upper chip, the stacked interconnect layer comprising a compliant dielectric material and an interconnect structure embedded in the compliant dielectric material, the interconnect structure comprising one or more via capture pads connected to the associated input/output pads on the top surface of the thin upper chip; and

a stacked thin chip on the stacked interconnect layer, the stacked thin chip comprising one or more microsystem devices with associated input/output pads on the top surface of the stacked thin chip that are connected to the one or more via capture pads in the stacked interconnect layer by conductive vias through the stacked thin chip.

3. The microsystem-on-a-chip of claim 1, wherein the interconnect layer has a thickness of less than 50 microns.

4. The microsystem-on-a-chip of claim 1, wherein the compliant dielectric material is a polymer.

5. The microsystem-on-a-chip of claim 4, wherein the polymer is benzocyclobutene.

6. The microsystem-on-a-chip of claim 1, wherein the thin upper chip has a thickness of less than 120 microns.

7. The microsystem-on-a-chip of claim 1, wherein the interconnect structure further comprises at least one passive component.

8. The microsystem-on-a-chip of claim 7, wherein the at least one passive component comprises a thin-film resistor.

9. The microsystem-on-a-chip of claim 7, wherein the at least one passive component comprises a multi-layer capacitor.

10. The microsystem-on-a-chip of claim 7, wherein the at least one passive component comprises a spiral inductor.

11. The microsystem-on-a-chip of claim 1, wherein the interconnect structure comprises copper.

12. The microsystem-on-a-chip of claim 1, wherein the one or more via capture pads are sized to control the alignment tolerance of the thin upper chip.

13. A method for fabricating a plurality of microsystems-on-a-chip, comprising:

providing a bottom wafer comprising a plurality of chips, each chip comprising one or more microsystem devices with associated input/output pads on the top surface of the bottom wafer;

forming an interconnect layer on the top surface of the bottom wafer, the interconnect layer comprising a compliant dielectric material and an interconnect structure embedded in the compliant dielectric material, the interconnect structure comprising one or more via capture pads connected to the associated input/output pads on the top surface of the bottom wafer;

bonding a thin upper wafer to the interconnect layer, the thin upper wafer comprising a plurality of chips, each chip comprising one or more microsystem devices with associated input/output pads on the top surface of the thin upper wafer that are connected to the one or more via capture pads in the interconnect layer by conductive vias through the thin upper wafer; and

singulating the plurality of chips from the bottom wafer, the interconnect layer and the thin wafer.

14. The method of claim 13, further comprising:

forming hollow vias in the thin upper wafer prior to bonding the thin upper wafer to the interconnect layer;

etching the hollow vias through to the one or more via capture pads in the interconnect layer after bonding the thin upper wafer to the interconnect layer; and

metallizing the hollow vias to provide the conductive vias.

15. The method of claim 13, further comprising:

forming hollow vias in the thin upper wafer through to the one or more via capture pads in the interconnect layer after bonding the thin upper wafer to the interconnect layer; and

metallizing the hollow vias to provide the conductive vias.

16. A method for aligned bonding of a thin upper wafer to a bottom wafer, comprising:

providing the bottom wafer;

depositing an interconnect layer on the top surface of the thick bottom wafer;

providing a thick upper wafer;

attaching a thick carrier wafer to the top surface of the thick upper wafer with a thermal release tape having a thermal release temperature;

thinning the bottom surface of the thick upper wafer to provide a thin upper wafer;

bonding the bottom surface of the thin upper wafer to the exposed surface of the interconnect layer; and

heating the bonded wafers to above the thermal release temperature to release the thermal release tape and the carrier wafer from the thin upper wafer.