SEMICONDUCTOR DEVICES WITH GRADED DOPANT REGIONS

• US 20070158790A1
• Filed: 01/12/2007
• Published: 07/12/2007
• Est. Priority Date: 09/03/2004
• Status: Active Grant

• Current Assignee: Greenthread, LLC
• Original Assignee: Rao Gr
• Inventors: Rao, G.R.
• Granted Patent: US 8,421,195 B2
• Time in Patent Office: Days
• US Class Current: 257/655
• CPC Class Codes: H01L 27/0214 for internal polarisation, e.g. I2L
• CPC Class Codes: H01L 27/14643 Photodiode arrays; MOS imagers
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/36 characterised by the concentration or distribution of impurities in the bulk material within semiconductor regions H01L29/06
• CPC Class Codes: H01L 29/7395 Vertical transistors, e.g. vertical IGBT
• CPC Class Codes: H10B 12/01 Manufacture or treatment
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND

Abstract

Most semiconductor devices manufactured today, have uniform dopant concentration, either in the lateral or vertical device active (and isolation) regions. By grading the dopant concentration, the performance in various semiconductor devices can be significantly improved. Performance improvements can be obtained in application specific areas like increase in frequency of operation for digital logic, various power MOSFET and IGBT ICS, improvement in refresh time for DRAM'"'"'s, decrease in programming time for nonvolatile memory, better visual quality including pixel resolution and color sensitivity for imaging ICs, better sensitivity for varactors in tunable filters, higher drive capabilities for JFET'"'"'s, and a host of other applications.

Claims

1. A semiconductor device with graded dopant concentration in the active region, to aid carrier movement from emitter to collector.

2. A semiconductor device with graded dopant concentration in the active region, to aid carrier movement from source to drain.

3. A semiconductor device with graded dopant concentration in the well regions, to aid carrier movement away from the active surface regions, towards the substrate.

4. A semiconductor device with graded dopant concentration in the substrate region to aid carrier movement away from the active surface regions, deeper towards the substrate.

5. A semiconductor device with at least one each of dopant concentration of both donor and acceptor, to optimize the operating performance of the device.

6. A semiconductor device with at least one graded dopant concentration fabricated with ion implantation, to provide an aiding or retarding electric field locally in a monolithic integrated circuit.

7. A semiconductor device with at least one graded dopant concentration in an epitaxial layer.

8. A semiconductor device where one layer of dopant from one wafer, is transferred to another wafer having either same polarity or different polarity dopant through wafer bonding or similar processes.