INTEGRATED CIRCUIT PACKAGE-IN-PACKAGE SYSTEM

• US 20070158813A1
• Filed: 03/23/2007
• Published: 07/12/2007
• Est. Priority Date: 02/04/2005
• Status: Active Grant

• Current Assignee: Stats Chippac Pte. Ltd. (JCET Group Co., Ltd.)
• Original Assignee: Jong Kook Kim
• Inventors: Kim, Jong Kook
• Granted Patent: US 7,429,798 B2
• Time in Patent Office: Days
• US Class Current: 257/686
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/11 Manufacturing methods
• CPC Class Codes: H01L 2224/1134 Stud bumping, i.e. using a wire-bonding apparatus
• CPC Class Codes: H01L 2224/13 of an individual bump connector
• CPC Class Codes: H01L 2224/1308 being stacked
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48464 the other connecting portion not on the bonding area also being a ball bond, i.e. ball-to-ball
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/81 using a bump connector
• CPC Class Codes: H01L 2224/85 : using a wire connector
• CPC Class Codes: H01L 2224/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/0651 : Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06517 : Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06524 : Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
• CPC Class Codes: H01L 2225/06541 : Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 2225/06575 : Auxiliary carrier between devices, the carrier having no electrical connection structure
• CPC Class Codes: H01L 2225/06582 : Housing for the assembly, e.g. chip scale package [CSP]
• CPC Class Codes: H01L 2225/107 : Indirect electrical connections, e.g. via an interposer, a flexible substrate, using TAB
• CPC Class Codes: H01L 23/3114 : the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/3128 : the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/5385 : Assembly of a plurality of insulating substrates
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/03 : all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 25/162 : the devices being mounted on two or more different substrates
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00011 : Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00013 : Fully indexed content
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19107 : off-chip wires
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

A package-in-package system is provided including forming a top substrate having a first integrated circuit electrically connected thereto and mounting a second integrated circuit over the first integrated circuit. The system includes forming first electrical connectors on the second integrated circuit and encapsulating the second integrated circuit in a first encapsulant with the first electrical connectors exposed. The system includes mounting the second integrated circuit over a bottom substrate with the first electrical connectors electrically connected thereto and encapsulating the top substrate and the first encapsulant in a second encapsulant.

Claims

1. A package-in-package system comprising:

forming a top substrate having a first integrated circuit electrically connected thereto;

mounting a second integrated circuit under the first integrated circuit;

forming first electrical connectors on and under the second integrated circuit;

encapsulating the second integrated circuit in a first encapsulant with the first electrical connectors exposed;

mounting the second integrated circuit over a bottom substrate with the first electrical connectors electrically connected thereto; and

encapsulating the top substrate and the first encapsulant in a second encapsulant.

2. The system as claimed in claim 1 further comprising encapsulating the first integrated circuit in a third encapsulant.

3. The system as claimed in claim 1 further comprising electrically connecting the top and bottom substrates.

4. The system as claimed in claim 1 further comprising:

forming second electrical connectors on the bottom substrate; and

electrically connecting the first electrical connectors to the second electrical connectors.

5. The system as claimed in claim 1 further comprising forming third electrical connectors on the bottom of the bottom substrate electrically connected to the top substrate and the first electrical connectors.

6. A package-in-package system comprising:

forming a top substrate having a first set of integrated circuits electrically connected by wire bonds thereto;

mounting a second set of integrated circuits under the first set of integrated circuits;

forming stud bumps on and under the second set of integrated circuits;

encapsulating the second set of integrated circuits in a first encapsulant with the stud bumps exposed;

flipping the second set of integrated circuits over a bottom substrate to mount the second set of integrated circuits with the stud bumps electrically connected thereto; and

encapsulating the top substrate and the first encapsulant in a second encapsulant.

7. The system as claimed in claim 6 further comprising encapsulating the first set of integrated circuits in a third encapsulant.

8. The system as claimed in claim 6 further comprising electrically connecting the top and bottom substrates by wire bonding.

9. The system as claimed in claim 6 further comprising:

forming solder balls on the bottom substrate; and

electrically connecting the stud bumps to the solder balls.

10. The system as claimed in claim 6 further comprising forming a ball grid array on the bottom of the bottom substrate electrically connected to the top substrate and the stud bumps.

11. A package-in-package system comprising:

a top substrate;

a first integrated circuit electrically connected to the top substrate;

a second integrated circuit under the first integrated circuit;

first electrical connectors on and under the second integrated circuit;

a first encapsulant encapsulating the second integrated circuit with the first electrical connectors exposed;

a bottom substrate having the second integrated circuit electrically connected thereto by the first electrical connectors; and

a second encapsulant encapsulating the top substrate.

12. The system as claimed in claim 11 further comprising a third encapsulant encapsulating the first integrated circuit.

13. The system as claimed in claim 11 further comprising wire bonds electrically connecting the top and bottom substrates.

14. The system as claimed in claim 11 further comprising:

second electrical connectors on the bottom substrate; and

the first electrical connectors electrically connected to the second electrical connectors.

15. The system as claimed in claim 11 further comprising third electrical connectors on the bottom of the bottom substrate and electrically connected to the top substrate and the first electrical connectors.

16. A package-in-package system comprising:

a top substrate;

a first set of integrated circuits electrically connected by wire bonds to the top substrate;

a bottom substrate

a second set of integrated circuits mounted under the first set of integrated circuits, the second set of integrated circuits having stud bumps thereon and thereunder, and encapsulated in a first encapsulant with the stud bumps exposed, the second set of integrated circuits over the bottom substrate with the stud bumps electrically connected thereto; and

a second encapsulant encapsulating the top substrate and the first encapsulant.

17. The system as claimed in claim 16 further comprising a third encapsulant encapsulating the first set of integrated circuits.

18. The system as claimed in claim 16 further comprising bond wires electrically connecting the top and bottom substrates.

19. The system as claimed in claim 16 further comprising solder balls on the bottom substrate electrically connected to the stud bumps.

20. The system as claimed in claim 16 further comprising a ball grid array on the bottom of the bottom substrate electrically connected to the top substrate and the stud bumps.