METHODS OF MANUFACTURING A THREE-DIMENSIONAL SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICES FABRICATED THEREBY

• US 20070158831A1
• Filed: 01/09/2007
• Published: 07/12/2007
• Est. Priority Date: 01/10/2006
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: SUH, Dong-Chul, BAE, Dae-Lok, CHA, Yong-Won
• Granted Patent: US 7,605,022 B2
• Time in Patent Office: Days
• US Class Current: 257/724
• CPC Class Codes: H01L 21/76254 with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 23/34 Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements thermal treatment apparatus H01L21/00

Abstract

A method of fabricating a three-dimensional semiconductor device is provided along with a three-dimensional semiconductor device fabricated thereby. The method includes forming a heat conductive plug to channel heat away from devices on a substrate, while high temperature processes are performed on a stacked semiconductor layer. The ability to use high temperature processes on the stacked semiconductor layer without adversely effecting devices on the substrate allows the formation of a high quality single-crystalline stacked semiconductor layer. The high quality single-crystalline semiconductor layer can then be used to fabricate improved thin film transistors.

Claims

1. A method of manufacturing a semiconductor device comprising:

forming an insulation layer on a first semiconductor substrate;

forming an opening through the insulation layer, the opening exposing a region of the first semiconductor substrate;

forming a heat conductive plug in the opening;

forming a separation layer in a second semiconductor substrate, the separation layer separating a surface layer and a bulk layer on the second semiconductor substrate;

bonding the insulation layer of the first substrate to the surface layer of the second substrate;

delaminating the bulk layer from the surface layer at the separation layer;

heat treating the surface layer while conducting heat away from the surface layer primarily through the heat conductive plug into the first semiconductor substrate; and

forming an upper device on the surface layer.

2. The method of claim 1, wherein the heat conductive plug has a higher heat conductivity than the insulation layer.

3. The method of claim 1, wherein forming the insulation layer on the first semiconductor substrate comprises:

forming a lower discrete device on the first semiconductor substrate; and

forming the insulation layer on the first semiconductor substrate substantially covering the lower device.

4. The method of claim 3, wherein forming a lower discrete device comprises forming a bulk transistor.

5. The method of claim 1, wherein forming the separation layer comprises implantation of impurity ions into the first semiconductor substrate.

6. The method of claim 5, wherein the impurity ions are hydrogen ions.

7. The method of claim 6, wherein the hydrogen ions are implanted with a dose of about 1×

10¹⁶ atoms/cm² to about 1×

10¹⁷ atoms/cm².

8. The method of claim 1, further comprising creating a hydrophilic surface on the insulation layer and the surface layer.

9. The method of claim 8, wherein creating a hydrophilic surface comprises exposing the insulation layer and the surface layer to a plasma including a plasma source gas.

10. The method of claim 9, wherein the plasma source gas is oxygen gas.

11. The method of claim 8, wherein creating a hydrophilic surface comprises:

cleaning the insulation layer and the surface layer using a wet process; and

exposing the insulation layer and the surface layer to hydrofluoric acid.

12. The method of claim 1, wherein bonding the insulation layer to the surface layer comprises:

placing the insulation layer in contact with the surface layer; and

heating the insulation layer and surface layer at a temperature of about 100°

C. to about 600°

C.

13. The method of claim 1, wherein delaminating the bulk layer from the surface layer comprises:

heating the separation layer at a temperature of about 200°

C. to about 900°

C.; and

removing the separation layer and the bulk layer from the surface layer.

14. The method of claim 13, wherein heating the separation layer is performed in a nitrogen environment.

15. The method of claim 1, wherein heat treating the surface layer is performed at a temperature of about 600°

C. to about 1200°

C.

16. The method of claim 1, further comprising, after delaminating:

blanket etching the surface layer.

17. The method of claim 16, wherein etching the surface layer comprises a wet etch process, a dry etch process, or a chemical-mechanical polishing (CMP) process.

18. The method of claim 16, further comprising cooling the first semiconductor substrate while heat treating.

19. The method of claim 18, wherein cooling comprises placing the first semiconductor substrate in contact with a heat sink.

20. The method of claim 19, wherein the heat sink comprises a cooling stage having a coolant medium.

21. The method of claim 16, wherein heat treating the surface layer is performed in an environment comprising nitrogen gas, hydrogen gas, or oxygen gas.

22. The method of claim 16, wherein heat treating the surface layer comprises placing the surface layer in a furnace, exposing the surface layer with a halogen lamp, or exposing the surface layer with a laser.

23. The method of claim 1, further comprising, after delaminating:

forming a sacrificial oxide layer on the surface layer; and

removing the sacrificial oxide layer.

24. The method of claim 23, wherein forming a sacrificial oxide layer is performed at a temperature range of about 500°

C. to 1000°

C. for a time period of about thirty (30) minutes to four (4) hours.

26. The method of claim 24, wherein the second region of the first semiconductor substrate comprises a scribe line area.

25. A method of manufacturing a semiconductor device, the method comprising:

forming a lower device in a first region of a first semiconductor substrate;

forming an insulation layer on the first semiconductor substrate, the insulation layer having the lower device therein;

forming an opening through the insulation layer, exposing a second region of the first semiconductor substrate;

forming a heat conductive plug in the opening, the heat conductive plug having a higher heat conductivity than the insulation layer;

forming a separation layer in a second semiconductor substrate, wherein the separation layer separates a surface layer and a bulk layer on the second semiconductor substrate and the surface layer comprises a single-crystalline material;

performing a surface treatment on the insulation layer and the surface layer, wherein the surface treatment creates a hydrophilic surface on the insulation layer and the surface layer;

bonding the insulation layer to the surface layer;

delaminating the bulk layer from the surface layer at the separation layer;

heat treating the surface layer to remove any artifacts of the forming of and delaminating at the separation layer from the surface layer, wherein heat treating comprises;

placing the first semiconductor substrate on a cooling stage; and

applying heat to the surface layer thereby channeling heat away from the surface layer through the heat conductive plug into the first semiconductor substrate toward the cooling stage; and

then, forming an upper device on the surface layer.

27. A semiconductor device, comprising:

a semiconductor substrate having an active region defined by a field region;

a lower discrete device disposed on the semiconductor substrate, the lower discrete device formed on the active region;

an insulation layer disposed on the semiconductor substrate substantially covering the lower device;

a semiconductor surface layer overlying the insulation layer;

an upper discrete device formed on the semiconductor surface layer; and

a heat conductive plug extending through the insulation layer, the heat conductive plug formed in a region of the semiconductor substrate other than the active region and the field region, the heat plug configured to conduct heat from the semiconductor surface layer primarily therethrough into the semiconductor substrate away from the lower device during heat treatment.

28. The device of claim 27, wherein the semiconductor surface layer comprises single-crystalline semiconductor material.

29. The device of claim 27, wherein the lower device is a transistor, capacitor, or resistor.

30. The device of claim 27, wherein the lower device comprises a bulk transistor.

31. The device of claim 30, further comprising a resistor or a capacitor disposed on the bulk transistor.

32. The device of claim 27, wherein the upper device is a thin film transistor (TFT).

33. The device of claim 32, wherein the heat conductive plug comprises a material having a heat conductivity higher than that of the insulation layer.

34. The device of claim 33, wherein the heat conductive plug comprises a metal, carbon nanotube or a polysilicon material.

35. The device of claim 27, wherein the heat conductive plug is formed in a region between adjacent cell blocks, where no discrete device is formed.

36. The device of claim 27, wherein the heat conductive plug is formed in a scribe line area of the semiconductor substrate.

37. The device of claim 27, wherein a top of the heat conductive plug is in contact with a bottom of the semiconductor surface layer and a bottom of the heat conductive plug is in contact with a top surface of the semiconductor substrate.

38. A method of manufacturing a semiconductor device, the method comprising:

providing a first semiconductor substrate having an active region, defined by a field region, and a dummy region including regions of the first semiconductor substrate that are not the active region and the field region;

forming an insulation layer having a heat conductive plug and a lower discrete device on the first semiconductor substrate, the heat conductive plug formed within the dummy region of the first semiconductor substrate, the lower discrete device formed in the active region;

placing a second semiconductor substrate over the first semiconductor substrate;

heat treating the second semiconductor substrate while conducting heat away from the second semiconductor substrate primarily through the heat conductive plug formed within the dummy region into the first semiconductor substrate; and

forming an upper device on the heat-treated second semiconductor substrate.

39. The method of claim 38, wherein the first semiconductor substrate includes a plurality of cell blocks spaced apart from each other by the dummy region, the cell blocks each including a cell region and a peripheral circuit region.

40. The method of claim 38, wherein the second semiconductor substrate comprises a single crystalline material.

41. A method of manufacturing a semiconductor device, the method comprising:

forming an insulation layer on a first semiconductor substrate;

forming an opening through the insulation layer, the opening exposing a region of the first semiconductor substrate;

forming a heat conductive plug in the opening;

forming a separation layer in a second semiconductor substrate, the separation layer separating a surface layer and a bulk layer on the second semiconductor substrate;

bonding the insulation layer of the first substrate to the surface layer of the second substrate;

delaminating the bulk layer from the surface layer at the separation layer;

forming a sacrificial oxide layer on the surface layer;

removing the sacrificial oxide layer; and

forming an upper device on the surface layer.

42. The method of claim 41, wherein forming a sacrificial oxide layer is performed at a temperature range of about 500°

C. to 1000°

C. for a time period of about thirty (30) minutes to four (4) hours.

43. The method of claim 41, wherein delaminating the bulk layer comprises applying a mechanical force to at least one of the bulk layer and the surface layer.