High output current buffer

• US 20070159255A1
• Filed: 01/10/2006
• Published: 07/12/2007
• Est. Priority Date: 01/10/2006
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Smith, Steven
• Granted Patent: US 7,411,455 B2
• Time in Patent Office: Days
• US Class Current: 330/267
• CPC Class Codes: H03F 3/3076 with symmetrical driving of the end stage

Abstract

A bipolar high output current buffer is disclosed using a negative feedback current mirror to supply the base drive to an output transistor. Small quiescent currents are used wherein the buffer demonstrates low quiescent power dissipation. The current mirror supplies the incremental base drive to the output transistor to support high output currents. When the output drive may source or sink the high output currents, two current mirrors may be used, one for each of the source and the sinking circuitry. This invention provides for minimal loss of dynamic range.

Claims

1. A high current output buffer comprising:

a first bipolar transistor with its emitter producing the high output current;

a second bipolar transistor having the same polarity as the first, the emitter of the second transistor connected to the collector of the first transistor, and the collector of the second transistor connected to a first voltage source;

the base of the first transistor coupled to the collector of a third transistor of the opposite polarity with respect to the first and second transistors;

the emitter of the third transistor connected to a first resistor whose distal end is coupled to a second voltage source;

the emitter of the third transistor also coupled to the emitter of a fourth transistor of common polarity with the third transistor;

the collector of the fourth transistor coupled to its base and to a first current source;

the base of the second transistor coupled to a resistor whose distal end is coupled to the second voltage source;

the base of the second transistor also coupled to the emitter of a fifth transistor of common polarity to the third and fourth transistors;

the collector of the fifth transistor coupled to a second current source;

the bases of the fourth and the fifth transistors are coupled together; and

the base of the third transistor coupled to the collector of the fifth transistor, wherein the fourth and fifth transistors form a current mirror, and wherein the third, fourth and fifth transistors form a negative feedback loop, and where any incremental base drive for the first transistor to support an incremental current at the emitter of the first transistor is supplied from the collector of the third transistor.

2. The high output current buffer of claim 1 wherein the polarity of the first and second transistors are PNP, the polarity of the third, fourth, and fifth transistors are NPN, the first voltage source is equal to or negative compared to the second voltage source, and further comprising a capacitor coupled between the base of the third transistor and a return path.

3. The high output current buffer of claim 1 wherein the polarity of the first and second transistors are NPN, the polarity of the third, fourth, and fifth transistors are PNP, and the first voltage source is equal to or positive compared to the second voltage source.

4. The high output current buffer of claim 1 further comprising:

a sixth transistor of common polarity with the third, fourth and fifth transistors, the emitter of the sixth transistor coupled to the base of the first transistor, its emitter also coupled to a third current source, and the base of the sixth transistor coupled to an input signal.

5. A high current output buffer comprising:

a first PNP with its emitter coupled to a first current source, the current source coupled to a positive voltage source, Vcc;

a first NPN with its emitter coupled to a second current source, the second current source coupled to a voltage source less positive than Vcc, this less positive voltage source labeled Vee;

wherein the collector of the first PNP is coupled to Vee, and the collector of the first NPN is coupled to Vcc, and wherein the bases of these transistors are coupled together and are arranged to accept an input signal;

the emitter of the first PNP is coupled to the base of a second NPN and the emitter of the first NPN is coupled to the base of a second PNP, the emitters of the second PNP and the second NPN coupled together to provide an output signal;

a third NPN with its collector coupled to Vcc and emitter coupled to the collector of the second NPN;

a third PNP with its collector coupled to Vee and its emitter coupled to the collector of the second PNP;

a first current mirror with a first input and a first output, each arranged to sink current signals, wherein the first input is coupled to the base of the third PNP and the first output is coupled to the base of the second PNP;

the first current mirror arranged to work near Vee; and

wherein a change in the output signal current is reflected back to the first current mirror that supplies the necessary base drive to the second and third PNP transistors to accommodate the change in the output signal current delivered.

6. The circuit of claim 5 further comprising a second current mirror with a second input and a second output, each arranged to source current signals, wherein the second input is coupled to the base of the third NPN and the second output is coupled to the base of the second NPN, and wherein the second current mirrors are arranged to operate near Vcc, and wherein a change in the output signal current is reflected back to the second current mirror that supplies the necessary base drive to the second and third PNP transistors to accommodate the change in the output signal current delivered.

7. The circuit of claim 6 wherein the second current mirror comprises:

a fourth PNP with its collector arranged as the second output;

a first resistor coupled from the emitter of the fourth PNP to Vcc;

a fifth PNP with its base connected to the base of a sixth PNP, and the collector of the fifth and the sixth PNP'"'"'s each coupled to current sources coupled to Vee, the fifth and sixth PNP'"'"'s forming a current mirror;

the emitter of the sixth PNP coupled to a resistor to Vcc, wherein the emitter of the sixth PNP is arranged as the second input;

the collector of the sixth PNP connected to the base of the fourth PNP;

the base of the fifth PNP coupled to its collector forming a diode connected transistor, and the emitter of the fifth PNP coupled to the emitter of the fourth PNP; and

a capacitor coupled from the collector of the sixth PNP to a low impedance return path.

8. The circuit of claim 7 further comprising a buffer located between the collector of the sixth PNP transistor and the base of the fourth PNP.

9. The circuit of claim 5 wherein the first current mirror comprises:

a fourth NPN with its collector arranged as the first output;

a first resistor connected from the emitter of the fourth NPN to Vee;

a fifth NPN with its base coupled to the base of a sixth NPN, and the collector of the fifth and the sixth NPN'"'"'s each coupled to current sources connected to Vcc, the fifth and sixth NPN'"'"'s forming a current mirror;

the emitter of the sixth NPN coupled to a resistor to Vee, wherein the emitter of the sixth NPN is arranged as the first input;

the collector of the sixth NPN coupled to the base of the fourth NPN;

the base of the fifth NPN coupled to its collector forming a diode coupled transistor, and the emitter of the fifth NPN coupled to the emitter of the fourth NPN, and

a capacitor coupled from to the collector of the sixth NPN to a low impedance return path.

10. The circuit of claim 9 further comprising a buffer located between the collector of the sixth NPN transistor and the base of the fourth NPN.