APPARATUS AND METHOD FOR PROCESSING IMAGE SIGNAL WITHOUT REQUIRING HIGH MEMORY BANDWIDTH

• US 20070159642A1
• Filed: 01/08/2007
• Published: 07/12/2007
• Est. Priority Date: 01/10/2006
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: CHOI, Ho-youn
• Granted Patent: US 7,885,485 B2
• Time in Patent Office: Days
• US Class Current: 358/1.200
• CPC Class Codes: G06T 3/40 Scaling of whole images or parts thereof, e.g. expanding or contracting
• CPC Class Codes: H04N 21/4316 for displaying supplemental content in a region of the screen, e.g. an advertisement in a separate window
• CPC Class Codes: H04N 21/440263 by altering the spatial resolution, e.g. for displaying on a connected PDA
• CPC Class Codes: H04N 5/21 Circuitry for suppressing or minimising disturbance, e.g. moiré or halo
• CPC Class Codes: H04N 5/45 Picture in picture , e.g. displaying simultaneously another television channel in a region of the screen
• CPC Class Codes: H04N 7/012 Conversion between an interlaced and a progressive signal for graphics images G09G2310/0229

Abstract

An image signal processor for processing an input image signal to output an output image signal includes an input unit receiving the input image signal, a noise removal unit removing noise from the input image signal, and a scaler reducing, maintaining or magnifying the image size of the input image signal. The scaler directly receives the input image signal from the input unit or the noise removal unit in response to a route control signal, reduces the image size of the input image signal when the image size of the input image signal is larger than the image size of the output image signal and stores the image signal with a reduced image size in a memory. The scaler maintains or magnifies the image size of the image signal stored in the memory and outputs the image signal with a maintained or magnified image size as the output image signal.

Claims

1. An image signal processor for processing an input image signal to output an output image signal comprising:

an input unit receiving the input image signal;

a noise removal unit removing noise from the input image signal; and

a scaler reducing, maintaining or magnifying an image size of an input image signal input thereto,

wherein the scaler directly receives the input image signal from the input unit or the noise removal unit in response to a route control signal, reduces the image size of the input image signal when the image size of the input image signal is larger than the image size of the output image signal to generate a reduced image and stores the reduced image signal in a memory,

wherein the scaler maintains or magnifies an image size of an image signal stored in the memory and outputs the image signal with a maintained or magnified image size as the output image signal.

2. The image signal processor of claim 1, wherein the noise removal unit directly receives the input image signal from the input unit in response to the route control signal without the input image signal passing through the memory.

3. The image signal processor of claim 2, wherein the input unit or the noise removal unit directly transmits the input image signal to the scaler in response to the route control signal without the input image signal passing through the memory.

4. The image signal processor of claim 1, wherein when the image signal stored in the memory is composed of a plurality of lines of video data, the scaler reads one line of video data of the plurality of lines from the memory for each single memory access to output the output image signal.

5. The image signal processor of claim 1, wherein when the input image signal is composed of n lines of video data and the output image signal is composed of m lines of video data, where m is smaller than n, the scaler reduces the image size of the input image signal to correspond to the m lines to generate the reduced image signal and stores the reduced image signal in the memory.

6. The image signal processor of claim 5, wherein the scaler maintains the image size of the image signal stored in the memory and outputs the reduced image signal as the output image signal.

7. The image signal processor of claim 6, wherein one line of video data read by the scaler from the memory, corresponds to one line of video data of the output image signal.

8. The image signal processor of claim 1, wherein when the input image signal is composed of n lines of video data and the output image signal is composed of m lines of video data, where m is larger than n, the input image signal is transmitted from the input unit or the noise removal unit to the memory and stored in the memory.

9. The image signal processor of claim 8, wherein the scaler magnifies the image size of the image signal stored in the memory and outputs the image signal with a magnified image size as the output image signal.

10. The image signal processor of claim 9, wherein one line of video data read by the scaler from the memory, corresponds to two or more lines of video data of the output image signal.

11. The image signal processor of claim 1, further comprising:

a deinterlacing unit for deinterlacing an interlaced image signal.

12. The image signal processor of claim 11, wherein the input image signal passes through the deinterlacing unit in response to the route control signal when the input image signal is an interlaced image signal, and the input image signal does not pass through the deinterlacing unit in response to the route control signal when the input image signal is a progressive image signal.

13. A method of processing an image signal, comprising:

directly transmitting an input image signal from an input unit or a noise removal unit to a scaler when an image size of the input image signal is larger than an image size of the output image signal;

reducing the image size of the input image signal directly transmitted to the scaler to correspond to the image size of the output image signal to generate a reduced image signal and storing the reduced image signal in a memory; and

reading the reduced image signal from the memory and outputting the read image signal as the output image signal.

14. The method of claim 13, wherein the directly transmitting of the input image signal from the input unit or the noise removal unit to the scaler comprises:

directly transmitting the input image signal from the input unit to the noise removal unit without the input image signal passing through the memory to generate a filtered image signal; and

directly transmitting the filtered image signal from the noise removal unit to the scaler without the filtered image signal passing through the memory.

15. The method of claim 13, wherein, in directly transmitting the input image signal from the input unit or the noise removal unit to the scaler, the input image signal is directly transmitted from the input unit to the scaler in response to a route control signal.

16. The method of claim 13, wherein, when the input image signal is an interlaced image signal, the interlaced image signal passes through a deinterlacing unit to be deinterlaced.

17. The method of claim 13, wherein, in reducing the image size of the input image signal directly transmitted to the scaler to correspond to the image size of the output image signal to generate a reduced image signal and storing the reduced image signal in the memory, the reduced image signal is stored as a plurality of lines of video data in the memory.

18. The method of claim 17, wherein, in reading the reduced image signal from the memory and outputting the read image signal as the output image signal, the scaler reads one line of video data of the plurality of lines of video data from the memory for each single memory access.

19. An image signal processor for processing a main input image signal and a sub input image signal for forming a PIP image comprising:

a first input unit receiving the main input image signal;

a second input unit receiving the sub input image signal;

a noise removal unit removing noise from an image signal input thereto;

a deinterlacing unit deinterlacing an image signal input thereto;

first and second scalers scaling image sizes of the main and sub input image signals;

first and second multiplexers controlling routes of the main and sub input image signals; and

an output multiplexer receiving a main output image signal or a sub output image signal output from the first or second scaler,

wherein the main input image signal and the sub input image signal are directly transmitted to the noise removal unit or the first and second scalers without passing through a memory, and the first or second scaler reduces the image size of the main input image signal or the sub input image signal to correspond to an image size of the main output image signal or the sub output image signal and stores the image signal with a reduced image size in the memory.

20. The image signal processor of claim 19, wherein the main input image signal or the sub input image signal, which has an image size reduced by the first or second scaler, is stored in the form of a plurality of lines of video data in the memory.

21. The image signal processor of claim 20, wherein the first or second scaler reads one line of video data of the plurality of lines of video data from the memory for each single memory access.

22. The image signal processor of claim 19, wherein the main input image signal is transmitted from the first input unit to the noise removal unit via the second multiplexer to generate a filtered main image signal.

23. The image signal processor of claim 22, wherein the filtered main image signal is transmitted to the first scaler when the image size of the main input image signal is larger than the image size of the main output image signal.

24. The image signal processor of claim 23, wherein the first scaler reduces an image size of the filtered main image signal to correspond to the image size of the main output image signal to generate a reduced main image signal and stores the reduced main image signal in the memory.

25. The image signal processor of claim 24, wherein the reduced main image signal stored in the memory is output as the main output image signal via the first scaler and the output multiplexer.

26. The image signal processor of claim 19, wherein the deinterlacing unit deinterlaces an image signal received from the memory when the image signal stored in the memory is an interlaced image signal and stores the deinterlaced image signal in the memory.

27. The image signal processor of claim 19, wherein the sub input image signal is transmitted from the second input unit to the second scaler via the first multiplexer.

28. The image signal processor of claim 27, wherein the second scaler reduces the image size of the sub input image signal to correspond to the image size of the sub output image signal to generate a reduced sub image signal and stores the reduced sub image signal in the memory.

29. The image signal processor of claim 28, wherein the reduced sub image signal stored in the memory is output as the sub output image signal via the second scaler and the output multiplexer.

30. The image signal processor of claim 19, wherein the output multiplexer outputs only the main output image signal when the image signal processor is operated in a normal display mode and outputs both the main output image signal and the sub output image signal when the image signal processor is operated in a PIP mode.