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Programming method for flash memory capable of compensating reduction of read margin between states due to high temperature stress

  • US 20070159892A1
  • Filed: 08/31/2006
  • Published: 07/12/2007
  • Est. Priority Date: 01/12/2006
  • Status: Active Grant
First Claim
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1. A programming method for a flash memory device having a plurality of memory cells storing multi-bit data indicating one of a plurality of states, the programming method comprising:

  • programming selected memory cells with multi-bit data to have one of the plurality of states;

    detecting programmed memory cells arranged within a predetermined region of a threshold voltage distribution, the region corresponding to at least two of the plurality of states,wherein predetermined regions of the respective at least two of the plurality of states are selected by one of a first verify voltage and a read voltage and a second verify voltage, the first verify voltage being lower than the second verify voltage and higher than the read voltage; and

    simultaneously programming detected memory cells of the at least two of the plurality of states to have a threshold voltage being equivalent to or higher than the second verify voltage corresponding to each of the plurality of states.

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