Wide dynamic range and high speed voltage mode sensing for a multilevel digital non-volatile memory

• US 20070159904A1
• Filed: 03/22/2007
• Published: 07/12/2007
• Est. Priority Date: 01/14/1999
• Status: Active Grant

• Current Assignee: Hieu Tran, Sakhawat Khan
• Original Assignee: Hieu Tran, Sakhawat Khan
• Inventors: Tran, Hieu, Khan, Sakhawat
• Granted Patent: US 7,471,581 B2
• Time in Patent Office: Days
• US Class Current: 365/207
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5635 Erasing circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 11/5678 using amorphous/crystalline phase transition storage elements
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/24 Bit-line control circuits
• CPC Class Codes: G11C 16/28 using differential sensing or reference cells, e.g. dummy cells
• CPC Class Codes: G11C 2211/5634 Reference cells
• CPC Class Codes: G11C 27/005 with non-volatile charge storage, e.g. on floating gate or MNOS

Abstract

A high speed voltage mode sensing is provided for a digital multibit non-volatile memory integrated system. An embodiment has a local source follower stage followed by a high speed common source stage. Another embodiment has a local source follower stage followed by a high speed source follower stage. Another embodiment has a common source stage followed by a source follower. An auto zeroing scheme is used. A capacitor sensing scheme is used. Multilevel parallel operation is described.

Claims

1-52. -52. (canceled)

53. A data storage system comprising:

a plurality of reference memory subarrays, each reference memory subarray comprising a plurality of reference memory cells, each memory cell being configurable to store one of a plurality of reference signal levels; and

a plurality of reference sense amplifiers, each reference sense amplifier being selectively coupled to a corresponding subarray;

a capacitor configured to capacitively sense content of a memory cell.

127. The data storage system of claim 53 wherein each reference sense amplifier is selectively coupled to a plurality of reference memory subarrays to capacitively sense an output of a memory cell.

128. The data storage system of claim 53 further comprising a reference array operatively coupled to the reference memory subarrays and configurable to provide stored reference signals used for programming and reading selected reference memory cells, the stored reference signals corresponding to detected reference signals.

129. The data storage system of claim 128 wherein each reference sense amplifier is selectively coupled to a plurality of reference memory subarrays to capacitively sense an output of a memory cell.

130. The data storage system of claim 53 wherein the reference sense amplifier capacitively detects a signal on a bitline and a reference signal and generates an output signal indicative of the comparison between said detected signal in a selected reference cell and said detected reference signal.

131. The data storage system of claim 130 wherein each reference sense amplifier is selectively coupled to a plurality of reference memory subarrays to capacitively sense an output of a memory cell.

132. The data storage system of claim 130 further comprising a reference array operatively coupled to the reference memory subarrays and configurable to provide stored reference signals used for programming and reading selected reference memory cells, the stored reference signals corresponding to detected reference signals.

133. The data storage system of claim 132 wherein each reference sense amplifier is selectively coupled to a plurality of reference memory subarrays to capacitively sense an output of a memory cell.

134. The data storage system of claim 53 wherein each reference sense amplifier being selectively coupled to a group of sense amplifiers to capacitively sense an output associated with said group of sense amplifiers.

135. The data storage system of claim 53 wherein each reference sense amplifier being coupled to a group of bitlines to capacitively detect a signal on a bitline and to a reference array to capacitively detect a reference signal, and to generate an output signal indicative of the comparison between said detected signal in a selected memory cell and said detected reference signal.

54. (canceled)

55. A data storage system comprising:

a plurality of reference memory subarrays, each reference memory subarray comprising a plurality of reference memory cells, each reference memory cell being configurable to store one of a plurality of reference signal levels; and

a plurality of reference sense amplifiers, each sense reference amplifier being selectively coupled to a reference memory subarray to sense with offset autozeroing content of a reference memory cell.

136. The data storage system of claim 55 wherein each reference sense amplifier autozeros an input and output in order to zero out offset of reference sense circuitry.

137. The data storage system of claim 55 wherein at least one reference sense amplifier includes a circuit for coupling inputs of the at least one reference sense amplifier to an output signal in response to an autozero signal.

138. The data storage system of claim 137 wherein each reference sense amplifier autozeros an input and output in order to zero out offset of reference sense circuitry.

139. The data storage system of claim 55 further comprising a reference array operatively coupled to the reference memory subarrays and configurable to provide stored reference signals used for programming and reading selected reference memory cells, the stored reference signals corresponding to detected reference signals.

140. The data storage system of claim 139 wherein each reference sense amplifier autozeros an input and output in order to zero out offset of reference sense circuitry.

141. The data storage system of claim 139 wherein at least one reference sense amplifier includes a circuit for coupling inputs of the at least one reference sense amplifier to an output signal in response to an autozero signal.

142. The data storage system of claim 141 wherein each reference sense amplifier auto zeros an input and output in order to zero out offset of reference sense circuitry.

143. The data storage system of claim 55 further comprising a circuit to set an input and an output of reference circuitry in response to an autozero signal.

144. The data storage system of claim 143 wherein reference circuitry autozeros an input and an output in order to zero out an offset of the reference circuitry.

56-126. -126. (canceled)