Serial media independent interface

• US 20070160087A1
• Filed: 03/14/2007
• Published: 07/12/2007
• Est. Priority Date: 06/02/1998
• Status: Abandoned Application

• Current Assignee: Cisco Technology, Inc. (Cisco Systems, Inc.)
• Original Assignee: Cisco Technology, Inc. (Cisco Systems, Inc.)
• Inventors: Bechtolsheim, Andreas, Findlater, Stewart
• Application Number:
  US11/724,533
• Publication Number:
  US 20070160087A1
• Time in Patent Office: Days
• US Class Current: 370/498
• CPC Class Codes: H04J 3/0685 Clock or time synchronisation in a node; Intranode synchronisation
• CPC Class Codes: H04L 12/40006 Architecture of a communication node current supply arrangements H04L12/10; intermediate storage or scheduling H04L49/90
• CPC Class Codes: H04L 12/413 with random access, e.g. carrier-sense multiple-access with collision detection [CSMA-CD]
• CPC Class Codes: H04L 7/0008 Synchronisation information channels, e.g. clock distribution lines

Abstract

A 10/100Base-T MAC to PHY interface requiring only two wires (pins) per port, with two additional global wires: a clock wire (pin), and a synchronization wire (pin) represents a reduction in the number of pins associated with each port and is achieved by time-division multiplexing wherein each time-division multiplexed wire combines a plurality of definitions from the conventional 100Base-T interface specified by IEEE 802.3u (clause 22). As a result, each port has its own pair of associated time-division multiplexed wires (pins) and the addition of each port simply requires two additional wires. According to a preferred embodiment of the present invention, information normally transferred on sixteen wires in a conventional 100Base-T interface at 25 MHz is time-division multiplexed onto two wires (corresponding to two pins) that transfer data at 125 MHz, five times the speed of conventional interfaces. Importantly, this multiplexing is done on a port by port basis. Therefore, the number of pins required for a MAC to transceiver interface is two times the number of ports plus two instead of sixteen times the number of ports, and the addition of each additional port requires only two more wires (pins).

Claims

1. A multi-port Ethernet device, comprising:

a MAC chip having one or more ports;

a PHY chip having one or more ports; and

a 10/100Base-T interface connecting said MAC and PHY chips, said interface comprising,

two time-division multiplexed wires per port on each chip, each time-division multiplexed wire configured for conveying time-division multiplexed signals having different definitions, and

two global wires configured for conveying clock and synchronization pulse signals for up to all of the ports on each chip.

2. The Ethernet device of claim 1, wherein said 10/100Base-T interface is configured to convey all required signals between said MAC chip and said PHY chip with 2n+2 wires, where n is the number of ports on each chip connected by the interface.

3. The Ethernet device of claim 1, wherein said two time-division multiplexed wires comprise a transmit wire and a receive wire.

4. The Ethernet device of claim 3, wherein said transmit wire is configured to convey transmit enable, transmit data, and transmit error signals in a segment from said MAC chip to said PHY chip.

5. The Ethernet device of claim 4, wherein said receive wire is configured to convey receive data valid, carrier sense, and receive data signals in a segment from said PHY chip to said MAC chip.

6. The Ethernet device of claim 5, wherein said transmit and receive wires are configured to convey 8 bits of data per segment.

7. The Ethernet device of claim 1, wherein said clock signal has a frequency of about 125 MHz.

8. The Ethernet device of claim 1, wherein, in operation, said time-division multiplexed signals are conveyed on said time-division multiplexed wires in about 12.5 MHz time slots.

9. The Ethernet device of claim 1, wherein, in operation, said synchronization pulse is asserted one out of every ten clocks.

10. The Ethernet device of claim 1, wherein said PHY chip comprises an elasticity FIFO.

11. The Ethernet device of claim 10, wherein the capacity of said elasticity FIFO is calculated as follows:

FIFO size=2*(maximum frame in bits)*(end station error+local error).

12. A 10/100Base-T interface connecting MAC and PHY chips each having one or more ports, said interface comprising:

two time-division multiplexed wires per port on each chip, each time-division multiplexed wire configured for conveying time-division multiplexed signals having different definitions, and

two global wires configured for conveying clock and synchronization pulse signals for up to all of the ports on each chip.

13. The interface of claim 12, wherein said 10/100Base-T interface is configured to convey all required signals between said MAC chip and said PHY chip with 2n+2 wires, where n is the number of ports on each chip connected by the interface.

14. The interface of claim 12, wherein said two time-division multiplexed wires comprise a transmit wire and a receive wire.

15. The interface of claim 14, wherein said transmit wire conveys a transmit enable, transmit data, and transmit error signals in a segment from said MAC chip to said PHY chip.

16. The interface of claim 15, wherein said receive wire conveys receive data valid, carrier sense, and receive data signals in a segment from said PHY chip to said MAC chip.

17. The interface of claim 16, wherein said transmit and receive wires are configured to convey 8 bits of data per segment.

18. The interface of claim 12, wherein said clock signal has a frequency of about 125 MHz.

19. The interface of claim 12, wherein, in operation, said time-division multiplexed signals are conveyed on said time-division multiplexed wires in about 12.5 MHz time slots.

20. The interface of claim 12, wherein, in operation, said synchronization pulse is asserted one out of every ten clocks.

21. A method of interfacing a MAC chip to a PHY chip in an Ethernet device, comprising:

conveying a first plurality of time-division multiplexed signals having different definitions from a MAC chip to a PHY chip over a 10/100Base-T transmit wire;

conveying a second plurality of time-division multiplexed signals having different definitions from the PHY chip to the MAC chip over a 10/100Base-T receive wire;

conveying a clock signal to said MAC chip and said PHY chip over a global clock wire; and

conveying a synchronization pulse signal to said MAC chip and said PHY chip over a global synchronization pulse wire.

22. The method of claim 21, wherein said 10/100Base-T interface conveys all required signals between said MAC chip and said PHY chip with 2n+2 wires, where n is the number of ports on each chip connected by the interface.

23. The method of claim 21, wherein said transmit wire conveys a transmit enable, transmit data, and transmit error signals in a segment from said MAC chip to said PHY chip.

24. The method of claim 23, wherein said receive wire conveys receive data valid, carrier sense, and receive data signals in a segment from said PHY chip to said MAC chip.

25. The method of claim 24, wherein said transmit and receive wires convey 8 bits of data per segment.

26. The method of claim 21, wherein said clock signal has a frequency of about 125 MHz.

27. The method of claim 21, wherein said time-division multiplexed signals are conveyed on said time-division multiplexed wires in about 12.5 MHz time slots.

28. The method of claim 21, wherein said synchronization pulse is asserted one out of every ten clocks.

29. The method of claim 21, wherein said PHY chip comprises an elasticity FIFO.

30. The method of claim 29, wherein the capacity of said elasticity FIFO is calculated as follows:

FIFO size=2*(maximum frame in bits)*(end station error+local error).

31. A method of interfacing a plurality of MAC chips in a 10/100Base-T Ethernet device, comprising:

conveying a first plurality of time-division multiplexed signals having different definitions from a first MAC chip to a second MAC chip over a first 10/100Base-T wire;

conveying a second plurality of time-division multiplexed signals having different definitions from the second MAC chip to the first MAC chip over a second 10/100Base-T wire;

conveying a clock signal to said first and second MAC chips over a global clock wire; and

conveying a synchronization pulse signal to said first and second MAC chips over a global synchronization pulse wire.

32. A multi-port Ethernet device, comprising:

a MAC chip having one or more ports;

a PHY chip having one or more ports; and

means for conveying all signals required for a 10/100Base-T interface between said MAC chip and said PHY chip with 2n+2 wires, where n is the number of ports on each chip connected by the interface.

33. A multi-port Ethernet media access control layer chip, comprising:

a 10/100Base-T interface for connecting said media access control layer chip with a physical layer chip, said interface comprising,

two time-division multiplexed pins per port on said media access control layer chip, each time-division multiplexed pin configured for conveying time-division multiplexed signals having different definitions, and

two global pins configured for conveying clock and synchronization pulse signals for up to all of the ports on said media access control layer chip.

34. The media access control layer chip of claim 33, wherein said 10/100Base-T interface is configured to convey all required signals between said MAC chip and said PHY chip with 2n+2 wires, where n is the number of ports on each chip connected by the interface.

35. The media access control layer chip of claim 33, wherein said two time-division multiplexed pins comprise a transmit pin and a receive pin.

36. The media access control layer chip of claim 35, wherein said transmit pin is configured to convey transmit enable, transmit data, and transmit error signals in a segment from said media access control layer chip to a physical layer chip.

37. The media access control layer chip of claim 36, wherein said receive pin is configured to convey receive data valid, carrier sense, and receive data signals in a segment from a physical layer chip to said media access control layer chip.

38. The media access control layer chip of claim 37, wherein said transmit receive pins are configured to convey 8 bits of data per segment.

39. The media access control layer chip of claim 33, wherein said clock signal has a frequency of about 125 MHz.

40. The media access control layer chip of claim 33, wherein, in operation, said time-division multiplexed signals are conveyed on said time-division multiplexed pins in about 12.5 MHz time slots.

41. The media access control layer chip of claim 33, wherein, in operation, said synchronization pulse is asserted one out of every ten clocks.

42. A multi-port Ethernet physical layer chip, comprising:

a 10/100 Base-T interface for connecting said physical layer chip with a media access control layer chip, said interface comprising,

two time-division multiplexed pins per port on said physical layer chip, each time-division multiplexed pin configured for conveying time-division multiplexed signals having different definitions, and

two global pins configured for conveying clock and synchronization pulse signals for up to all of the ports on said physical layer chip.

43. The physical layer chip of claim 42, wherein said 10/100Base-T interface is configured to convey all required signals between said MAC chip and said PHY chip with 2n+2 wires, where n is the number of ports on each chip connected by the interface.

44. The physical layer chip of claim 42, wherein said two time-division multiplexed pins comprise a transmit pin and a receive pin.

45. The physical layer chip of claim 44, wherein said transmit pin is configured to convey transmit enable, transmit data, and transmit error signals in a segment from a media access control layer chip to said physical layer chip.

46. The physical layer chip of claim 45, wherein said receive pin is configured to convey receive data valid, carrier sense, and receive data signals in a segment from said physical layer chip to a media access control layer chip.

47. The physical layer chip of claim 46, wherein said transmit and receive pins convey 8 bits of data per segment.

48. The physical layer chip of claim 42, wherein said clock signal has a frequency of about 125 MHz.

49. The physical layer chip of claim 42, wherein, in operation, said time-division multiplexed signals are conveyed on said time-division multiplexed pins in about 12.5 MHz time slots.

50. The physical layer chip of claim 42, wherein, in operation, said synchronization pulse is asserted one out of every ten clocks.

51. The physical layer chip of claim 42, wherein said physical layer chip further comprises an elasticity FIFO.

52. The physical layer chip of claim 51, wherein the capacity of said elasticity FIFO is calculated as follows:

FIFO size=2*(maximum frame in bits)*(end station error+local error).