Method and apparatus for varied format encoding and decoding of pixel data

• US 20070160139A1
• Filed: 12/30/2005
• Published: 07/12/2007
• Est. Priority Date: 12/30/2005
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Selwan, Pierre, Vasquez, Maximino
• Granted Patent: US 7,627,182 B2
• Time in Patent Office: Days
• US Class Current: 375/240.80
• CPC Class Codes: G06F 3/14 Digital output to display device ; Cooperation and interconnection of the display device with other functional units
• CPC Class Codes: G09G 2360/02 Graphics controller able to handle multiple formats, e.g. input or output formats
• CPC Class Codes: G09G 5/008 Clock recovery

Abstract

An apparatus, system, and method for encoding video pixels is provided in some embodiments. At least one encoder may encode a video pixel data as a symbol. A selection unit may select the symbol. A selection of the symbol is a function of a pixel format that is of one of a plurality of pixel formats employable the apparatus, system or method.

Claims

1. An apparatus, comprising:

an encoder that encodes a pixel of video data as a symbol; and

a selection unit that selects the symbol, wherein a selection of the symbol is a function of a pixel format that is of one of a plurality of pixel formats employable by the apparatus.

2. The apparatus of claim 1, further comprising a plurality of encoders that encode the pixel of video data as a one of a plurality of symbols, wherein each encoder has a different symbol encoding format.

3. The apparatus of claim 2, wherein the selection unit selects one of the plurality of symbols as a selected symbol.

4. The apparatus of claim 3, wherein the selection unit comprises a multiplexer.

5. The apparatus of claim 1, wherein a clock signal is generated as a function of the pixel format.

6. The apparatus of claim 5, wherein the clock signal is employed by a first unit that receives the pixel data and conveys the pixel data to at least one encoder;

and

wherein the clock signal is further employed by a second unit that outputs a selected symbol.

7. The apparatus of claim 1, further comprising a transmitter that transmits an output data derived from a selected symbol.

8. The apparatus of claim 7, wherein the output data derived from the selected symbol is a function of a parallel to serial conversion of the selected symbol.

9. The apparatus of claim 1, wherein a selected symbol corresponds to a given number of bits of video pixel data transmitted during a given time period.

10. The apparatus of claim 1, wherein a selected symbol comprises at least one extra bit more than in a correlated video pixel data.

11. An apparatus, comprising:

a selection unit that selects a decoding scheme for a symbol, wherein a selection of the decoding scheme is a function of at least a pixel format that is of one of a plurality of pixel formats employable the apparatus; and

at least one decoder that decodes the symbol as a video pixel data.

12. The apparatus of claim 11, further comprising a plurality of decoders that decode the symbol, wherein each decoder has a different decoding scheme.

13. The apparatus of claim 12, wherein the selection unit selects one of the plurality of decoding schemes.

14. The apparatus of claim 13, wherein the selection unit comprises a multiplexer.

15. The apparatus of claim 11, wherein a clock pulse is generated as a function of the pixel format.

16. The apparatus of claim 15, wherein the clock signal is employed by a first unit that receives the symbol and conveys symbol to the at least one decoder;

and

wherein the clock signal is further employed by a second unit that outputs the pixel data.

17. A method, comprising:

receiving a pixel format at a drain;

receiving a pixel symbol in an output data at the drain;

regenerating a pixel clock pulse from the output data and from the pixel format;

regenerating, at the drain, the pixel symbol from the output data; and

decoding a pixel data from the pixel symbol through a using of the pixel clock pulse.

18. The method of claim 17, further comprising:

selecting, at a source, the pixel format from a plurality of employable pixel formats;

receiving the pixel data at the source;

selecting an encoding scheme as a function of a selected pixel format; and

generating the pixel symbol at the source by applying the selected encoding scheme to the pixel data.

19. The method of claim 18, further comprising:

selecting, at the source, a second pixel format from a plurality of employable pixel formats; and

selecting, at the source, a second encoding scheme as a function of the second pixel format.

20. The method of claim 18, further comprising:

generating the pixel clock pulse as a function of the pixel format; and

conveying the video pixel data, as a function of the pixel clock pulse, to at least one encoder of a variable encoder, the encoder to correlate to the selected encoding scheme.

21. The method of claim 18, further comprising:

generating a pixel clock pulse at the source as a function of received data at the source, the received data correlating to the pixel symbol; and

conveying the link data and to at least one decoder of the variable decoder of the drain, the decoder to correlate to a selected decoding scheme; and

regenerating the pixel clock pulse from the link data.

22. The method of claim 18, wherein said output data comprises link data.

23. The method of claim 17, further comprising rendering the pixel data with use of the pixel clock pulse.

24. A system, comprising:

a motherboard;

a variable encoder integrated circuit coupled to the motherboard, wherein the variable encoder integrated circuit accepts a pixel format and a pixel data, and the variable encoder integrated circuit selects a symbol encoding scheme of the video pixel data; and

a variable transmission integrated circuit coupled to the motherboard, the variable transmission integrated circuit further coupled to the variable encoder integrated circuit, the variable transmission integrated circuit to transmit data corresponding to a symbol of a selected symbol coding scheme; and

a first double rate memory element coupled to the motherboard and the variable encoder integrated circuit; and

a second double rate memory element coupled to the motherboard an the variable transmission integrated circuit.

25. The system of claim 24, wherein a pixel clock pulse is generated as a function of the pixel format.