Liquid crystal display array board and method of fabricating the same

• US 20070161184A1
• Filed: 09/12/2006
• Published: 07/12/2007
• Est. Priority Date: 11/23/2005
• Status: Active Grant

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Mobile Display Company Limited (Samsung Electronics Co. Ltd.)
• Inventors: Kim, Do Young, Heo, Hae Jin
• Granted Patent: US 7,868,338 B2
• Time in Patent Office: Days
• US Class Current: 438/255
• CPC Class Codes: G02F 1/136213 Storage capacitors associated with the pixel electrode
• CPC Class Codes: G02F 2201/40 Arrangements for improving the aperture ratio
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors
• CPC Class Codes: Y10S 438/964 Roughened surface

Abstract

A liquid crystal display array board includes a plurality of gate wiring lines formed on a substrate and a plurality of data wiring lines crossing the plurality of gate wiring lines, a plurality of thin film transistors formed in areas defined by crossings of the gate wiring lines and the data wiring lines, a plurality of storage capacitor first electrodes that run parallel to the gate wiring lines and patterned to have concavo-convex patterns, a plurality of storage capacitor second electrodes integrated with the drain electrodes of the thin film transistors and formed on the storage capacitor first electrodes, and a plurality of pixel electrodes electrically connected to the drain electrodes.

Claims

1. A liquid crystal display array board comprising:

a plurality of gate wiring lines formed on a substrate and a plurality of data wiring lines crossing the plurality of gate wiring lines;

a plurality of thin film transistors formed in areas defined by crossings of the gate wiring lines and the data wiring lines;

a plurality of storage capacitor first electrodes parallel to the gate wiring lines and patterned to have concavo-convex patterns;

a plurality of storage capacitor second electrodes integrated with drain electrodes of the thin film transistors and formed on the storage capacitor first electrodes; and

a plurality of pixel electrodes electrically connected to the drain electrodes.

2. The liquid crystal display array board as claimed in claim 1, wherein the storage capacitor first electrodes are formed by substantially the same material as the gate wiring lines.

3. The liquid crystal display array board as claimed in claim 1, wherein the storage capacitor first electrodes are formed in substantially the same layer as the gate wiring lines.

4. The liquid crystal display array board as claimed in claim 1, wherein an insulating layer is formed between the storage capacitor first electrodes and the storage capacitor second electrodes.

5. The liquid crystal display array board as claimed in claim 4, wherein the insulating layer is a gate insulating layer.

6. The liquid crystal display array board as claimed in claim 1, wherein the concavo-convex patterns of the storage capacitor first electrodes are formed by exposing the regions in which the storage capacitor first electrodes are to be formed using a phase shift mask or a slit mask during a mask process.

7. The liquid crystal display array board as claimed in claim 1,

wherein the thin film transistors comprise a plurality of gate electrodes, a plurality of source electrodes, the drain electrodes, and a plurality of active layers,

wherein the source electrodes are connected to the data wiring lines, and

wherein the gate electrodes are connected to the gate wiring lines crossing the data wiring lines to define a plurality of pixel regions.

10. The method as claimed in claim 1, further comprising:

forming a plurality of pixel electrodes in the pixel regions defined by the crossings of the gate wiring lines and the data wiring lines on a protective layer.

11. The method as claimed in claim 10, wherein the pixel electrodes are electrically connected to drain electrodes of a plurality of thin film transistors through a plurality of contact holes formed in predetermined positions of the protective layer, the drain electrodes being integrated with the capacitor storage second electrodes.

8. A method of fabricating a liquid crystal display array board, the method comprising:

forming a plurality of gate wiring lines and a plurality of concavo-convex storage capacitor first electrodes on a substrate so that the storage capacitor first electrodes run parallel to the gate wiring lines;

forming an insulating layer on the gate wiring lines and the storage capacitor first electrodes;

forming a plurality of data wiring lines to cross the plurality of gate wiring lines; and

forming a plurality of storage capacitor second electrodes on the insulating layer so that the storage capacitor second electrodes overlap the storage capacitor first electrodes in predetermined regions.

9. The method as claimed in claim 8, wherein the concavo-convex patterns of the convavo-convex storage capacitor first electrodes are formed by exposing the regions in which the first storage capacitor electrodes are to be formed using a phase shift mask or a slit mask during a mask process.

12. A liquid crystal display array board comprising:

a substrate;

a gate wiring line on the substrate;

a data wiring line crossing the gate wiring line;

a thin film transistor in an area defined by a crossing of the gate wiring line and the data wiring line;

a storage capacitor first electrode parallel to the gate wiring line and patterned to have a concavo-convex pattern;

a storage capacitor second electrode integrated with a drain electrode of the thin film transistor and on the storage capacitor first electrode; and

a pixel electrode electrically connected to the drain electrode.

13. The liquid crystal display array board as claimed in claim 12, wherein the storage capacitor first electrode is formed by substantially the same material as the gate wiring line.

14. The liquid crystal display array board as claimed in claim 12, wherein the storage capacitor first electrode is formed in substantially the same layer as the gate wiring line.

15. The liquid crystal display array board as claimed in claim 12, wherein an insulating layer is formed between the storage capacitor first electrode and the storage capacitor second electrode.

16. The liquid crystal display array board as claimed in claim 15, wherein the insulating layer is a gate insulating layer.

17. The liquid crystal display array board as claimed in claim 12, wherein the concavo-convex pattern of the storage capacitor first electrode is formed by using a phase shift mask or a slit mask during a mask process.

18. The liquid crystal display array board as claimed in claim 12,

wherein the thin film transistor comprises a gate electrode, a source electrode, the drain electrode, and an active layer,

wherein the source electrode is formed as a part of the data wiring line, and

wherein the gate electrode is connected to the gate wiring line crossing the data wiring line to define a pixel region.

19. The liquid crystal display array board as claimed in claim 12,

wherein the pixel electrode is formed on a protective layer, and

wherein the pixel electrode is electrically connected to the drain electrode through a contact hole formed in the protective layer.