High k gate stack on III-V compound semiconductors

• US 20070161214A1
• Filed: 01/06/2006
• Published: 07/12/2007
• Est. Priority Date: 01/06/2006
• Status: Abandoned Application

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Koester, Steven, Sadana, Devendra, Kiewra, Edward, Webb, David, Fompeyrine, Jean
• Application Number:
  US11/327,675
• Publication Number:
  US 20070161214A1
• Time in Patent Office: Days
• US Class Current: 438/483
• CPC Class Codes: H01L 21/02148 the material containing hafnium, e.g. HfSiOx or HfSiON
• CPC Class Codes: H01L 21/02181 the material containing hafnium, e.g. HfO2
• CPC Class Codes: H01L 21/02271 deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition H01L21/02266 takes precedence
• CPC Class Codes: H01L 21/28158 Making the insulator
• CPC Class Codes: H01L 21/3145 formed by deposition from a gas or vapour
• CPC Class Codes: H01L 21/31645 Deposition of Hafnium oxides, e.g. HfO2
• CPC Class Codes: H01L 21/3205 Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers manufacture of electrodes H01L21/28
• CPC Class Codes: H01L 21/32051 Deposition of metallic or metal-silicide layers
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A method of forming a high k gate stack (dielectric constant of greater than that of silicon dioxide) on a surface of a III-V compound semiconductor, such GaAs, is provided. The method includes subjecting a III-V compound semiconductor material to a precleaning process which removes native oxides from a surface of the III-V compound semiconductor material; forming a semiconductor, e.g., amorphous Si, layer in-situ on the cleaned surface of the III-V compound semiconductor material; and forming a dielectric material having a dielectric constant that is greater than silicon dioxide on the semiconducting layer. In some embodiments, the semiconducting layer is partially or completely converted into a layer including at least a surface layer that is comprised of AO_xN_y prior to forming the dielectric material. In accordance with the present invention, A is a semiconducting material, preferably Si, x is 0 to 1, y is 0 to 1 and x and y are both not zero.

Claims

1. A method of forming a material stack on a III-V compound semiconductor comprising:

removing native oxides from a III-V compound semiconductor material to provide a treated surface;

forming a semiconducting layer in-situ on said treated surface of said III-V compound semiconductor material; and

forming a dielectric material having a dielectric constant that is greater than silicon dioxide on said semiconducting layer.

2. The method of claim 1 wherein said removing said native oxides comprises desorption at a temperature of about 600°

C. or greater.

3. The method of claim 1 wherein said removing said native oxides comprises a plasma H process.

4. The method of claim 1 wherein said semiconducting layer is formed by epitaxy.

5. The method of claim 1 further comprising completely or partially converting the semiconducting layer into a AO_xN_y layer, wherein A is a semiconducting material, x is 0 to 1, y is 0 to 1 and x and y are both not zero, prior to forming the dielectric material.

6. The method of claim 1 wherein each of said steps is performed in-situ.

7. The method of claim 1 wherein each of said steps is performed at a temperature of less than 300°

C.

8. A method of forming a material stack on a III-V compound semiconductor comprising:

removing native oxides from a III-V compound semiconductor material to provide a treated surface;

forming a semiconducting layer in-situ on said treated surface of said III-V compound semiconductor material;

converting at least an upper surface region of said semiconducting layer to a region comprised of AO_xN_y wherein A is a semiconducting material, x is from 0 to 1, y is from 0 to 1 and x and y are both not zero; and

forming a dielectric material having a dielectric constant that is greater than silicon dioxide on the upper surface region of said semiconducting layer.

9. The method of claim 8 wherein said removing said native oxides comprises desorption at a temperature of about 600°

C. or greater.

10. The method of claim 8 wherein said removing said native oxides comprises a plasma H process.

11. The method of claim 8 wherein said semiconducting layer formed by epitaxy.

12. The method of claim 8 wherein each of said steps is performed in-situ.

13. The method of claim 8 wherein each of said steps is performed at a temperature of less than 300°

C.

14. A semiconductor structure comprising:

a III-V compound semiconductor material having a surface that is essentially free of oxides;

a semiconducting layer located on said surface, wherein an interface is present between the III-V compound semiconductor material and the semiconducting layer that has an interface state density of about 10¹² cm<sup>−

2</sup> eV<sup>−

1</sup> or less; and

a dielectric material having dielectric constant greater than that of silicon dioxide located on said semiconducting layer.

15. The semiconductor structure of claim 14 wherein said III-V compound semiconductor material includes an upper layer and a lower layer, wherein said upper layer has a wider-band gap than said lower layer.

16. The semiconductor structure of claim 14 wherein said semiconducting layer is amorphous.

17. The semiconductor structure of claim 14 wherein said semiconducting layer is Si.

18. The semiconductor structure of claim 14 wherein said semiconducting layer includes at least a surface region of AO_xN_y wherein A is a semiconducting material, x is from 0 to 1, y is from 0 to 1, both x and y are not zero and said dielectric material is located on said surface region of AO_xN_y.

19. The semiconductor structure of claim 14 wherein said semiconducting layer is replaced completely by an AO_xN_y layer wherein A is a semiconducting material, x is from 0 to 1 and y is from 0 to 1 and said dielectric material is located on said AO_xN_y layer.

20. The semiconductor structure of claim 14 wherein said dielectric material is a Hf-based dielectric.

21. The semiconductor structure of claim 14 further comprising an electrode or electrode stack on said dielectric material.

22. The semiconductor structure of claim 14 wherein said dielectric material is a gate dielectric of at least one field effect transistor device.

23. A method of enhancing the activation of implanted dopants within a III/V compound semiconductor material comprising:

providing a semiconducting cap layer atop a III/V compound semiconductor that has a surface that is essentially free of oxides, said III/V compound semiconductor including n-type dopants, p-type dopants or both; and

annealing the dopants to provide at least one activated dopant region in said III/V compound semiconductor.