Software assisted nested hardware transactions

• US 20070162520A1
• Filed: 12/30/2005
• Published: 07/12/2007
• Est. Priority Date: 12/30/2005
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Saha, Bratin, Adl-tabatabai, Ali-Reza, Petersen, Leaf
• Granted Patent: US 7,730,286 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 11/141 for bus or memory accesses

Abstract

A method and apparatus for efficiently executing nested transactions is herein described. Hardware support for execution of transactions is provided. Additionally, through the use of logging previous values immediately before a current nested transaction in a local memory and storage of a stack of handlers associated with a hierarchy of transactions, nested transactions are potentially efficiently executed. Upon a failure, abort, or invalidating event/access within a nested transaction, the state of variables or memory locations written to during execution of the nested transaction are rolled-back to immediately before the nested transaction, instead of all the way back to an original state of the variables or memory locations before an enclosing transaction. As a result, nested transactions may be re-executed within enclosing transactions, without flattening the enclosing and nested transactions to re-execute everything.

Claims

1. An apparatus comprising:

execution resources to execute first transaction and a second transaction nested in the first transaction;

a monitoring module to detect an invalidating event during execution of the second transaction;

a logging module to take a second-level snapshot of a second-level value in a memory location to be changed during execution of the second transaction; and

a roll-back module to roll-back the memory location to the second-level snapshot, upon the monitor module detecting an invalidating event during execution of the second transaction.

2. The apparatus of claim 1, wherein the execution resources includes logic to execute a begin transaction instruction at the start of the first transaction and the second transaction, and wherein the execution module also includes logic to execute an end transaction at the end of the first and the second transaction.

3. The apparatus of claim 1, wherein the monitoring module includes a cache coherency module to detect an invalidating event during execution of the second transaction.

4. The apparatus of claim 3, wherein the cache coherency module includes a bit associated with memory location, and wherein the bit is flipped to a first logical value upon detecting an invalidating event to represent an invalidating event occurred.

5. The apparatus of claim 1, wherein the logging module is also to store an abort handler stack including a second-level abort handler associated with the second transaction stacked on a first-level abort handler associated with the first transaction.

6. The apparatus of claim 5, wherein the roll-back module includes a control transfer module to transfer control to the second-level abort handler, if the monitoring module detects an invalidating event during execution of the second transaction.

7. The apparatus of claim 1, wherein the logging module includes a local memory to store the second-level snapshot.

8. The apparatus of claim 7, wherein the local memory is to store the second-level snapshot is stored in a stacked snapshot of the second-level snapshot stacked on a first-level snapshot taken before executing the first transaction.

9. The apparatus of claim 7, wherein the local memory is selected from a group consisting of a Random Access Memory (RAM), a Static RAM (SRAM), a Dynamic RAM (DRAM), a plurality of registers, and a plurality of latches.

10. An apparatus comprising:

a processor including

execution logic to execute a first transaction and a second transaction nested within the first transaction;

monitoring logic to determine if an invalidating access occurs during execution of the first or second transactions;

a local memory to store a first set of values from memory locations to be written to during execution of the first transaction and, a second set of values from memory locations to be written to during execution of the second transaction;

a handler module to restore the memory locations to be written to during execution of the second transaction to the second set of values, if an invalidating access occurs during execution of the second transaction.

11. The apparatus of claim 10, wherein the processor is selected from a group consisting of a host processor, a microprocessor, a processing core, a logical processor, and an embedded processor, a multi-threaded processor, and a multi-core processor.

12. The apparatus of claim 10, wherein execution logic includes logic to detect data conflicts, to buffer speculative updates, to make updates atomically visible at transaction commit, to execute instructions, and to operate on data.

13. The apparatus of claim 10, wherein a first transaction is demarcated by a first begin transaction instruction and a first end transaction instruction, and wherein the second transaction is demarcated by a second start transaction instruction and a second end transaction instruction between the first begin and end transaction instruction.

14. The apparatus of claim 10, wherein monitoring logic includes a flag for every line of memory in a cache of the processor to represent if an invalidating access occurred to a corresponding memory location during execution of the first or second transactions.

15. The apparatus of claim 14, wherein an invalidating access occurs during execution of the first transaction when an access by another resource to a memory location to be read from or written to occurs during pendancy of the first transaction, and wherein an invalidating access occurs during execution of the second transaction when an access by another resource to a memory location to be read from or written to occurs during pendancy of the second transaction.

16. The apparatus of claim 10, wherein the another resource is a resource, not executing the transaction, the resource being selected from a group consisting of a logical processor, a core, a thread, a software thread, a hardware thread, and a remote resource.

17. The apparatus of claim 10, wherein the first set of values from memory locations to be written to during execution of the first transaction are stored in the local memory before entering the first transaction, and wherein the second set of values from memory locations to be written to are stored in the local memory before entering the second transaction.

18. The apparatus of claim 10, wherein the first set of values from memory locations to be written to are stored in the local memory during execution of the first transaction immediately before the memory locations are written to, and wherein the second set of values from memory locations to be written to are stored in the local memory during execution of the second transaction immediately before the memory locations are written to.

19. The apparatus of claim 10, wherein the local memory is also to store a first abort handler associated with the first transaction and a second abort handler associated with the second transaction.

20. The apparatus of claim 19, wherein the handler module includes a default handler to transfer control of the processor to the first abort handler, if an invalidating access occurs during execution of the first transaction, and to transfer control of the processor to the second abort handler, if an invalidating access occurs during execution of the second transaction.

21. The apparatus of claim 20, wherein the second abort handler restores the memory locations to be written to during execution of the second transaction to the second set of values, after control is transferred to the second abort handler, if an invalidating access occurs during execution of the second transaction.

22. The apparatus of claim 21, wherein restoring the memory locations to be written to during execution of the second transaction to the second set of values comprises writing the second set of values, stored in the local memory, back into the memory locations to be written to during execution of the second transaction.

23. A system comprising:

a multi-resource microprocessor including

an execution unit to execute an outer transaction and an inner transaction nested within the outer transaction,

a local memory to store

a first set of values of a first plurality of locations, which are to be written to during execution of the inner transaction,

a first abort handler associated with the inner transaction, when executed, to restore the first plurality of locations to the first set of values;

a default handler, when executed by the execution unit, to initiate execution of the second abort handler, if an invalidating event occurs during execution of the second transaction; and

a system memory coupled to the multi-resource microprocessor to store a first plurality of instructions to be grouped as the outer instruction and a second plurality of instructions to be grouped as the inner transaction.

24. The system of claim 23, wherein the local memory is also to store

a second abort handler associated with the outer transaction, and

a second set of values of a second plurality of locations, which are to be written to during execution of the outer transaction.

25. The system of claim 23, wherein the default handler, when executed, is also to initial execution of the second abort handler, if an invalidating event occurs during execution of the outer transaction, and wherein the second abort handler, when executed, is to restore the second plurality of locations to the second set of values.

26. The system of claim 23, wherein the multi-resource processor includes a plurality of resources, and wherein the plurality of resources are a plurality of execution threads.

27. The system of claim 26, wherein an invalidating event occurring during execution of the second transaction includes an event initiated by one of the plurality of resources, not associated with the inner transaction, accessing one of the first plurality of locations during pendancy of the second transaction.

28. The system of claim 27, wherein a cache coherency protocol is used to determine if an invalidating event occurs during execution of the second transaction.

29. A method comprising:

executing a current level transaction nested within a previous level transaction; and

maintaining a log including a first state of a memory location at the previous level, which is to be written to during execution of the current level;

determining if an invalidating event occurs during execution of the current level transaction;

restoring the memory location to the first state of the memory location at the previous level, if an invalidating event is detected during execution of the current level transaction; and

merging the log with a second state of the memory location at the current level, if no invalidating event occurs during execution of the current level transaction.

30. The method of claim 29, wherein the log is stored in a local memory in a microprocessor.

31. The method of claim 29, wherein determining if an invalidating event occurs during execution of the current level transaction includes using a cache coherency protocol to determine if the invalidating event occurs during execution of the current level transaction.

32. The method of claim 29, further comprising maintaining a stack of a first abort handler associated with the current level transaction stacked on a second abort handler associated with the previous level transaction.

33. The method of claim 32, wherein restoring the memory location to the first state of the memory location at the previous level comprises:

popping the first abort handler off the stack;

transferring control to the first abort handler;

executing the first abort handler, wherein upon execution, the first abort handler restores the memory location with the first state of the memory location maintained in the log.

34. The method of claim 29, wherein merging the log with a second state of the memory location at a current level comprises:

appending the second state on the end of the log.

35. The method of claim 29, further comprising discarding the log upon committing the previous-level transaction, if the previous-level transaction is a top-level transaction.

36. A method comprising:

pushing an abort handler associated with a current nested transaction onto a stack of abort handlers;

logging a first value of a first memory location, which is to be changed during execution of the current nested transaction, in a local memory, before changing the value of the first memory location; and

determining with hardware if an invalidating event occurs during execution of the current nested transaction;

if an invalidating event occurs during execution of the current nested transaction transferring control to the abort handler associated with the current nested transaction, and

restoring the first memory location with the first value.

37. The method of claim 36, wherein the stack of abort handlers is stored in the local memory.

38. The method of claim 36, wherein logging a first value of a first memory location in a local memory before changing the value of the first memory location comprises:

logging the first value of the first memory location in a local memory before executing a first instruction in the current nested transaction.

39. The method of claim 36, wherein logging a first value of a first memory location in a local memory before changing the value of the first memory location comprises:

logging the first value of the first memory location in a local memory during execution of the current execution and immediately before the first memory location is changed.

40. The method of claim 36, wherein the hardware used to determine if an invalidating event occurs during execution of the current nested transaction includes a functional unit of a microprocessor selected from a group consisting of a cache, an advanced load address table (ALAT), and invalidating access tracking unit.

41. The method of claim 36, further comprising merging a log associated with the current nested transaction including the first value with an enclosing transaction log, if the current nested transaction is committed and the enclosing transaction is a nested transaction.

42. The method of claim 36, further comprising discarding a log associated with the current nested transaction including the first value, if the current nested transaction is committed and the enclosing transaction is a top-level transaction.