Method and apparatus for utilizing platform support for direct memory access remapping by remote DMA ("RDMA")-capable devices

• US 20070162641A1
• Filed: 12/28/2005
• Published: 07/12/2007
• Est. Priority Date: 12/28/2005
• Status: Active Grant

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Intel Corporation
• Inventors: Madukkarumukumana, Rajesh, Regnier, Greg, Oztaskin, Ali
• Granted Patent: US 7,702,826 B2
• Time in Patent Office: Days
• US Class Current: 710/22
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence

Abstract

A direct memory access (“DMA”) request specifies a target address within an input/output virtual address (“IOVA”) space. The DMA target is validated and data are transferred between the target identified by the IOVA and a second location. Chipsets and systems using embodiments of the invention are also described and claimed.

Claims

1. A method comprising:

receiving a direct memory access (“

DMA”

) target including a target address located within an input/output virtual address (“

IOVA”

) space;

validating the DMA target; and

transferring data between the DMA target identified by the IOVA and a second location.

2. The method of claim 1 wherein transferring comprises:

placing the IOVA on an address bus; and

exchanging data over a data bus.

3. The method of claim 1, further comprising:

warming a translation cache before transferring the data.

4. The method of claim 1, further comprising:

performing exactly one translation between the IOVA and a corresponding physical address.

5. The method of claim 4 wherein the validating operation is to be performed by a first hardware subsystem;

and the exactly one translation is to be performed by a second, different hardware subsystem.

6. The method of claim 5 wherein the first hardware subsystem is a remote DMA (“

RDMA”

) device and the second hardware subsystem is DMA address remapping logic.

7. A chipset comprising:

signaling circuitry to communicate with a remote peer;

remote direct memory access (“

RDMA”

) logic to execute a direct memory access (“

DMA”

) request from the remote peer;

protection checking logic to check a key and target address from the remote peer;

conversion logic to convert the target address to an input/output virtual address (“

IOVA”

); and

bus cycle generation logic to place the IOVA on an address bus and read corresponding data from a memory.

8. The chipset of claim 7 wherein the bus cycle generation logic places additional information on the address bus, the additional information including at least one of:

a bus identifier;

a device identifier; and

a function identifier.

9. The chipset of claim 7, further comprising:

translation-caching logic to obtain an IOVA-to-physical address translation from a local system; and

translation-cache invalidation logic to invalidate an entry in a translation cache if a signal is received from the local system.

10. The chipset of claim 7, further comprising:

logic to emulate a plurality of independent functional units, wherein an independent functional unit is to be allocated to a guest operating system.

11. The chipset of claim 10 wherein a bus cycle to access memory at an IOVA for a first emulated functional unit accesses a first memory location, and a bus cycle to access memory at the IOVA for a second emulated functional unit accesses a second, different memory location.

12. A system comprising:

a plurality of processors;

a communication interface;

a memory responsive to host physical addresses (“

HPAs”

) on an address bus; and

an address translation unit to translate an input-output virtual address (“

IOVA”

) from the communication interface to an HPA.

13. The system of claim 12, further comprising:

a memory management unit to manage data traffic between the plurality of processors and the memory; and

a data structure to control the address translation unit and the memory management unit.

14. The system of claim 12, further comprising:

remote direct memory access (“

RDMA”

) logic to receive an RDMA request through the communication interface;

protection checking logic to validate the RDMA request; and

bus control logic to place an IOVA on the address bus and access data in the memory.

15. The system of claim 12, further comprising:

a hypervisor to manage a plurality of guest operating systems; and

a guest operating system having a device driver to control the communication interface;

wherein the device driver is to provide an input/output virtual address (“

IOVA”

) to the communication interface;

the communication interface is to transfer data from the memory at a location identified by the IOVA; and

the address translation unit is to convert the IOVA to an HPA.