DMA Controller With Self-Detection For Global Clock-Gating Control
First Claim
1. A self-detection unit of a DMA controller, comprising:
- a detection unit that detects whether the internal state signals associated with a DMA transfer inside the DMA controller are active; and
a clock output unit that drives an enable signal to selectively turn on or off a globally gated clock according to the detection result of said detection unit, wherein said enable signal turns on said globally gated clock in response to an active state of the internal state signals, and said enable signal turns off said globally gated clock in response to an inactive state of the internal state signals.
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Abstract
A standby self-detection mechanism in a DMA controller which reduces the power consumption by dynamically controlling the on/off states of at least one clock tree driven by global clock-gating circuitry is disclosed. The DMA controller comprises a standby self-detection unit, a scheduler, at least one set of channel configuration registers associated with at least one DMA channel, and an internal request queue which holds already scheduled DMA requests that are presently outstanding in the DMA controller. The standby self-detection unit drives a signal to a global clock-gating circuitry to selectively turn on or off at least one of the clock trees to the DMA controller, depending on whether the DMA controller is presently performing a DMA transfer.
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Citations
20 Claims
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1. A self-detection unit of a DMA controller, comprising:
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a detection unit that detects whether the internal state signals associated with a DMA transfer inside the DMA controller are active; and
a clock output unit that drives an enable signal to selectively turn on or off a globally gated clock according to the detection result of said detection unit, wherein said enable signal turns on said globally gated clock in response to an active state of the internal state signals, and said enable signal turns off said globally gated clock in response to an inactive state of the internal state signals. - View Dependent Claims (2, 3, 4, 5)
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6. A DMA apparatus, comprising:
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a CPU bus interface that generates an enable signal to selectively turn on a global gated clock according to an internal state signal associated with an active request; and
a core unit that receives said global gated clock and is switched on in response to said global clock being turned on. - View Dependent Claims (7, 8, 9, 10, 11, 12, 13)
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14. A method of power management in a DMA controller, comprising:
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receiving and processing a DMA request;
detecting whether an internal state is active during said processing of said DMA request;
selectively turning on a global gated clock applied to a portion of said DMA controller according to the result of said detecting step. - View Dependent Claims (15, 16, 17, 18, 19, 20)
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Specification