Optimizing write and wear performance for a memory

• US 20070162700A1
• Filed: 12/16/2005
• Published: 07/12/2007
• Est. Priority Date: 12/16/2005
• Status: Active Grant

• Current Assignee: Microsoft Technology Licensing LLC (Microsoft Corporation)
• Original Assignee: Microsoft Corporation
• Inventors: Fortin, Michael, Reinauer, Robert
• Granted Patent: US 8,914,557 B2
• Time in Patent Office: Days
• US Class Current: 711/118
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0804 with main memory updating G06F12/0806 takes precedence
• CPC Class Codes: G06F 12/0808 with cache invalidating means G06F12/0815 takes precedence
• CPC Class Codes: G06F 12/0868 Data transfer between cache memory and other subsystems, e.g. storage devices or host systems
• CPC Class Codes: G06F 12/0873 Mapping of cache memory to specific storage devices or parts thereof
• CPC Class Codes: G06F 12/12 Replacement control
• CPC Class Codes: G06F 2212/1024 Latency reduction
• CPC Class Codes: G06F 2212/1036 Life time enhancement
• CPC Class Codes: G06F 2212/3042 being part of a memory device, e.g. cache DRAM
• CPC Class Codes: G06F 2212/305 being part of a memory device, e.g. cache DRAM
• CPC Class Codes: G06F 2212/7211 Wear leveling
• CPC Class Codes: G06F 3/0611 in relation to response time
• CPC Class Codes: G06F 3/0616 in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]
• CPC Class Codes: G06F 3/065 Replication mechanisms
• CPC Class Codes: G06F 3/0685 Hybrid storage combining heterogeneous device types, e.g. hierarchical storage, hybrid arrays

Abstract

Determining and using the ideal size of memory to be transferred from high speed memory to a low speed memory may result in speedier saves to the low speed memory and a longer life for the low speed memory.

Claims

1. An method of efficiently storing data where there is a plurality of data storage devices with a hierarchy of data storage speeds comprising:

receiving data to be stored on a lower speed data storage device;

storing the data in a high speed memory;

collecting additional data in the high speed memory until a preferred amount of data is stored that is destined for a particular lower speed data device;

storing the data in high speed memory until it is of a size that is appropriate write size for a particular storage device; and

once an appropriate write size of data for the particular device is stored in the high speed memory device, writing the data to the lower speed device.

2. The method of claim 1, further comprising keeping the data in high speed storage until a determination is made that the data no longer is needed in high speed storage.

3. The method of claim 1, wherein the data to be written to the low speed storage device is backed up on an additional low speed storage device.

4. The method of claim 1, wherein the low speed device is a flash storage device.

5. The method of claim 4, wherein the write size is the erase block size of the flash.

6. The method of claim 1, further comprising waiting until a period of low system activity to write to the low speed storage device.

7. The method of claim 1, further comprising warning a user that the data has yet to be written to the low speed memory device when a low speed memory device has been removed from the system before the data has been written from the high speed memory device to the low speed memory device.

8. The method of claim 7, wherein the user is presented the option to write the data from the high speed memory to the low speed memory before the low speed memory device is removed.

9. The method of claim 1, further comprising organizing the data in the high speed memory such that the write to the low speed memory is more efficient.

10. The method of claim 1, further comprising analyzing the data in the high speed memory to determine if any of the data has been replaced with newer data before the data is written to the low speed memory.

11. The method of claim 1, further comprising analyzing the data in the high speed memory to determine whether any of the data to be written to the low speed memory is duplicate data wherein the older duplicate data is not written to the low speed memory device.

12. The method of claim 1, further comprising invalidating blocks in the high speed memory when write operations impact those blocks before they have been committed to the low speed memory.

13. The method of claim 1, further comprising moving the data from the high speed memory to an additional memory that is lower speed that the high speed memory but higher speed than the low speed memory.

14. The method of claim 1, further comprising keeping an index of data in high speed memory that is to be written to low speed memory and if the data written to be written to the low speed device is resident in the high speed memory, serving read requests for the data from the high speed memory without regard as to whether the data has been written to low speed memory.

15. The method of claim 1, further comprising testing the low speed memory to determine the preferred write size for the low speed memory.

16. The method of claim 1, further comprising calculating the preferred write size to be related to the preferred erase size of the low speed memory.

17. A computer readable medium with computer executable instructions for efficiently storing data where there is a plurality of data storage devices with a hierarchy of data storage speeds, the computer instructions comprising:

receiving data to be stored on a lower speed data storage device;

storing the data in a high speed memory;

collecting additional data in the high speed memory until a preferred amount of data is stored that is destined for a particular lower speed data device;

storing the data in high speed memory until it is of a size that is appropriate write size for a particular storage device;

analyzing the data in the high speed memory to determine if any of the data has been replaced with newer data before the data is written to the low speed memory; and

once an appropriate write size of data for the particular device is stored in the high speed memory device, writing the data to the lower speed device.

18. The computer readable medium of claim 17, further comprising testing the low speed memory to determine the preferred erase and preferred write size for the low speed memory.

19. A computer system comprising a processor, an input output device and memory, the processor executing computer executable instructions and the memory storing computer executable where the computer executable instructions are for efficiently storing data where there is a plurality of data storage devices with a hierarchy of data storage speeds, the computer instructions comprising:

receiving data to be stored on a lower speed data storage device;

storing the data in a high speed memory;

testing the low speed memory to determine the preferred erase and preferred write size for the low speed memory collecting additional data in the high speed memory until a preferred amount of data is stored that is destined for a particular lower speed data device;

storing the data in high speed memory until it is of a size that is appropriate write size for a particular storage device;

analyzing the data in the high speed memory to determine if any of the data has been replaced with newer data before the data is written to the low speed memory; and

once an appropriate write size of data for the particular device is stored in the high speed memory device, writing the data to the lower speed device.

20. The computer system of claim 19, the computer executable instructions further comprising keeping an index of data in high speed memory that is to be written to low speed memory and if the data written to be written to the low speed device is resident in the high speed memory, serving read requests for the data from the high speed memory without regard as to whether the data has been written to low speed memory.