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Method and system for controlling an interleaver

  • US 20070162789A1
  • Filed: 02/20/2007
  • Published: 07/12/2007
  • Est. Priority Date: 04/17/1998
  • Status: Active Grant
First Claim
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1. A controller for an interleaver comprising:

  • a processor that is operative to receive a first signal, to receive a second signal, and to generate an interleaver control signal based on the first and second signals;

    wherein the first and second signals are selected from the group consisting of a signal to noise ratio signal, a data rate signal, and a bit error rate signal.

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