WIRELESS RADIO FREQUENCY TECHNIQUE DESIGN AND METHOD FOR TESTING OF INTEGRATED CIRCUITS AND WAFERS
First Claim
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1. Apparatus for testing an integrated circuit on a wafer, comprising:
- a) a test circuit formed on the wafer with the integrated circuit, the test circuit comprising;
i) configurable circuitry including a plurality of selectable sub-circuits;
ii) a control circuit configured to selectively enable at least one of the sub-circuits, and b) a test unit separate from the wafer, the test unit linked to the test circuit to transmit a signal to activate the test circuit, wherein the test circuit, when activated by the test unit, is configured to conduct a separate test of the integrated circuit for each sub-circuit selected by the control circuit and generate a test result signal.
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Abstract
Various embodiments are described herein for an apparatus and method for the wireless testing of Integrated Circuits and wafers. In one embodiment, the apparatus comprises a test unit external from the wafer and at least one test circuit that is fabricated on the wafer that contains the Integrated Circuit. The test unit transmits an RF signal to power the test circuit. The test circuit, comprising configurable circuitry, performs a series of parametric tests at the normal operating frequency of the Integrated Circuit and transmits the test results to the test unit for analysis.
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Citations
89 Claims
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1. Apparatus for testing an integrated circuit on a wafer, comprising:
- a) a test circuit formed on the wafer with the integrated circuit, the test circuit comprising;
i) configurable circuitry including a plurality of selectable sub-circuits;
ii) a control circuit configured to selectively enable at least one of the sub-circuits, and b) a test unit separate from the wafer, the test unit linked to the test circuit to transmit a signal to activate the test circuit, wherein the test circuit, when activated by the test unit, is configured to conduct a separate test of the integrated circuit for each sub-circuit selected by the control circuit and generate a test result signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43)
- a) a test circuit formed on the wafer with the integrated circuit, the test circuit comprising;
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44. A test circuit for testing an integrated circuit on a wafer, the test circuit formed on the wafer with the integrated circuit, the test circuit comprising:
- a) configurable circuitry including a plurality of sub-circuits; and
b) a control circuit configured to selectively enable at least one the sub-circuits wherein the test circuit is configured to conduct a separate test of the integrated circuit for each sub-circuit selected by the control circuit, and generate a test result signal. - View Dependent Claims (45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74)
- a) configurable circuitry including a plurality of sub-circuits; and
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75. A method of testing an integrated circuit on a wafer using a test circuit formed on the wafer with the integrated circuit, wherein the method comprises:
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(a) employing a test circuit comprising configurable circuitry including a plurality of sub-circuits, and a control circuit to selectively enable at least one of the sub-circuits to vary the configuration of the configurable circuitry, (b) activating the test circuit;
(c) selectively enabling the sub-circuits;
(d) producing a test result signal in response to each sub-circuit selected by the control circuit; and
,(e) analyzing the test result signal. - View Dependent Claims (76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89)
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Specification