Checksum generation apparatus and method thereof

• US 20070162820A1
• Filed: 12/10/2004
• Published: 07/12/2007
• Est. Priority Date: 12/16/2003
• Status: Abandoned Application

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Choi, Hyun-Seok
• Application Number:
  US10/584,093
• Publication Number:
  US 20070162820A1
• Time in Patent Office: Days
• US Class Current: 714/758
• CPC Class Codes: H03M 13/091 Parallel or block-wise CRC computation
• CPC Class Codes: H04L 1/0041 Arrangements at the transmitter end
• CPC Class Codes: H04L 1/0052 Realisations of complexity reduction techniques, e.g. pipelining or use of look-up tables
• CPC Class Codes: H04L 1/0061 Error detection codes
• CPC Class Codes: H04L 1/0072 Error control for data other than payload data, e.g. control data

Abstract

A checksum generation apparatus and method thereof. The checksum generation apparatus includes a control unit which, in response to information on a predetermined length, outputs a control signal when an amount of data corresponding to the predetermined length is received; an addition unit which receives data, performs an addition on the received data, and, in response to the control signal, outputs an addition result; and a conversion unit which converts the addition result to a checksum.

Claims

1. A checksum generation apparatus, comprising:

a control unit which, in response to information on a predetermined length, outputs a control signal when an amount of data corresponding to the predetermined length is received;

an addition unit which performs an addition on the received data, and, in response to the control signal, outputs an addition result; and

a conversion unit which converts the addition result to a checksum.

2. The checksum generation apparatus according to claim 1, wherein the checksum has a value of 16 bits.

3. The checksum generation apparatus according to claim 1, wherein the addition unit receives data in units of n*16 bits, where n is an integer greater than or equal to 2, and performs an addition on the received data.

4. The checksum generation apparatus according to claim 1, wherein the conversion unit divides the addition result into a sum and a carry, partitions the sum into 16-bit segments, and adds the 16-bit segments to the carry, thereby obtaining a final sum.

5. The checksum generation apparatus according to claim 4, wherein, when a carry occurs in the final sum, the conversion unit excludes the carry from the final sum and adds the carry to the carry-excluded final sum, thereby outputting a carry-added final sum.

6. The checksum generation apparatus according to claim 5, wherein the conversion unit outputs a 1'"'"'s complement value of the carry-added final sum as a 16-bit checksum.

7. The checksum generation apparatus according to claim 1, wherein the addition unit comprises:

an adder adding the received data in units of n*16 bits, where n is an integer greater than or equal to 2; and

a carry adder adding carries generated in the adder.

8. The checksum generation apparatus according to claim 1, wherein the conversion unit comprises:

a partial sum addition unit excluding a carry from the addition result, partitioning the carry-excluded addition result into 16-bit segments, adding the 16-bit segments, to obtain a partial sum;

a first adder adding the carry to the partial sum;

a second adder adding an addition result of the first adder and a carry occurring in the addition result of the first adder; and

a complement calculator outputting a 1'"'"'s complement value of the addition result of the second adder.

9. A method of generating a checksum, the method comprising:

adding input data until a predetermined control signal is received;

outputting a sum and a carry obtained from the addition result when the control signal is received; and

adding the sum and the carry and converting the added sum and carry to a checksum.

10. The method of generating a checksum according to claim 9, wherein the checksum is converted to a value of 16 bits.

11. The method of generating a checksum according to claim 9, wherein the control signal is output when an amount of data corresponding to input data length information is received.

12. The method of generating a checksum according to claim 9, wherein the data is received in units of n*16 bits, where n is an integer greater than or equal to 2 and an addition is performed on the received data.

13. The method of generating a checksum according to claim 9, wherein, the adding of the sum and the carry comprises:

partitioning the sum into 16-bit segments, and

adding the 16-bit segments to the carry, to obtain a final sum.

14. The method of generating a checksum according to claim 13, wherein, when a second carry occurs in the final sum, the second carry is excluded from the final sum and added to the carry-excluded final sum, to output a carry-added final sum.

15. The method of generating a checksum according to claim 14, further comprising:

outputting a 1'"'"'s complement value of the carry-added final sum as a 16-bit checksum.

16. The method of generating a checksum according to claim 9, wherein the outputting of the sum and carry comprises:

adding the received data in units of n*16 bits, where n is an integer greater than or equal to 2; and

adding carries generated in adding of the received data.

17. The method of generating a checksum according to claim 9, wherein the adding of the sum and the carry and the converting of the added sum and carry to a checksum comprises:

excluding the carry from the addition result, partitioning a carry-excluded addition result into 16-bit segments, and adding the 16-bit segments, to obtain a partial sum;

adding the carry to the partial sum to obtain a second addition result and a second carry;

adding the second addition result and the second carry to obtain a third addition result; and

outputting a 1'"'"'s complement value of the third addition result as the checksum.

18. A computer-readable storage medium storing a program executable by a computer, the program comprising instructions for enabling the computer to perform a method of generating a checksum, wherein the program comprises:

instructions for adding input data until a predetermined control signal is received;

instructions for outputting a sum and a carry obtained from an addition result when the control signal is received; and

instructions for adding the sum and the carry and converting the added sum and carry to a checksum.

19. An apparatus for generating a checksum, the apparatus comprising:

a first adder adding a predetermined number of bits of input data received in units of n*m bits, where n is a first integer greater than or equal to 2 and m is a second integer, to obtain a first sum having n*m bits and a first carry;

a partial sum calculator partitioning the first sum into n segments of m bits and adding the m-bit segments to obtain a second sum;

a second adder adding the second sum and the first carry to obtain a third sum and a second carry;

a third adder adding the third sum and the second carry to obtain a fourth sum; and

a complement calculator outputting a 1'"'"'s complement value of the fourth sum as an m-bit checksum.

20. An apparatus for generating a checksum, the apparatus comprising:

a first adder adding a predetermined number of bits of input data received in units of n*m bits, where n is a first integer greater than or equal to 2 and m is a second integer, to obtain a first sum having n*m bits and a first carry;

a partial sum calculator partitioning the first sum into n segments of m bits and adding the m-bit segments to obtain a second sum;

a second adder adding the second sum and the first carry to obtain a third sum; and

a complement calculator outputting a 1'"'"'s complement value of the third sum as an m-bit checksum.

21. A method of generating a checksum for input data received in units of n*m bits, where n is a first integer greater than or equal to 2 and m is a second integer n, the method comprising:

adding a predetermined number of the input data units without dividing the input data units into smaller units, to obtain a first sum having n*m bits and a first carry;

partitioning the first sum into n segments of m bits and adding the m-bit segments to obtain a second sum;

adding the second sum and the first carry to obtain a third sum; and

outputting a 1'"'"'s complement value of the third sum as an m-bit checksum.

22. The method of claim 21, wherein:

if a second carry is generated in the adding of the second sum and the first carry, the method further comprises;

adding the third sum and the second carry to obtain a fourth sum, and

replacing the third sum with the fourth sum in the outputting of the 1'"'"'s complement value as the m-bit checksum.