Method and apparatus to determine if a pattern is robustly manufacturable

• US 20070162888A1
• Filed: 02/28/2007
• Published: 07/12/2007
• Est. Priority Date: 09/29/2004
• Status: Active Grant

• Current Assignee: Synopsys Incorporated
• Original Assignee: Synopsys Incorporated
• Inventors: Beale, Daniel, Melvin III, Lawrence
• Granted Patent: US 7,739,651 B2
• Time in Patent Office: Days
• US Class Current: 716/51
• CPC Class Codes: G03F 1/36 Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes
• CPC Class Codes: G03F 1/80 Etching

Abstract

One embodiment provides a method to determine if a pattern is robustly manufacturable. During operation, the system may receive a first pattern and a design intent, wherein the first pattern is intended to generate the design intent. Next, the system may determine a second pattern using the design intent, wherein subjecting the second pattern to a second manufacturing process is expected to generate a third pattern that is substantially similar to the design intent. The system may then determine if a first semiconductor manufacturing process is capable of robustly manufacturing the second pattern. If the second pattern is not robustly manufacturable, the system may generate an indicator that indicates that the first pattern is not robustly manufacturable.

Claims

1. A method for determining if a pattern is robustly manufacturable, the method comprising:

receiving a first pattern and a design intent, wherein the first pattern is intended to generate the design intent;

determining a second pattern using the design intent, wherein subjecting the second pattern to a second manufacturing process is expected to generate a third pattern that is substantially similar to the design intent;

determining a second indicator which indicates whether the second pattern is robustly manufacturable by a first semiconductor manufacturing process; and

using the second indicator to generate a first indicator that indicates whether the first pattern is robustly manufacturable.

2. The method of claim 1, wherein the first pattern is intended to generate the design intent by:

subjecting the first pattern to the first semiconductor manufacturing process to obtain an intermediate pattern; and

subjecting the intermediate pattern to the second semiconductor manufacturing process to obtain a fourth pattern that is substantially similar to the design intent.

3. The method of claim 1, wherein determining the second pattern includes applying a second inverse-process-model to the design intent, wherein the second inverse-process-model models the inverse of the effect of the second semiconductor manufacturing process.

4. The method of claim 1,

wherein the first pattern is a mask pattern;

wherein the design intent is a pattern that is desired to be etched on the substrate layer;

wherein the first semiconductor manufacturing process is a photolithography process; and

wherein the second semiconductor manufacturing process is an etch process.

5. The method of claim 1, wherein determining the second indicator includes determining if the second pattern is realizable using the first manufacturing process.

6. The method of claim 1, wherein determining the second indicator includes determining a process window at an evaluation point in the second pattern.

7. The method of claim 6, wherein determining the process window includes convolving the second pattern with a first manufacturing sensitivity model, which models the sensitivity of the first semiconductor manufacturing process to process variations.

8. A computer-readable storage medium storing instructions that when executed by a computer cause the computer to perform a method for determining if a pattern is robustly manufacturable, the method comprising:

receiving a first pattern and a design intent, wherein the first pattern is intended to generate the design intent;

determining a second pattern using the design intent, wherein subjecting the second pattern to a second manufacturing process is expected to generate a third pattern that is substantially similar to the design intent;

determining a second indicator which indicates whether the second pattern is robustly manufacturable by a first semiconductor manufacturing process; and

using the second indicator to generate a first indicator that indicates whether the first pattern is robustly manufacturable.

9. The computer-readable storage medium of claim 8, wherein the first pattern is intended to generate the design intent by:

subjecting the first pattern to the first semiconductor manufacturing process to obtain an intermediate pattern; and

subjecting the intermediate pattern to the second semiconductor manufacturing process to obtain a fourth pattern that is substantially similar to the design intent.

10. The computer-readable storage medium of claim 8, wherein determining the second pattern includes applying a second inverse-process-model to the design intent, wherein the second inverse-process-model models the inverse of the effect of the second semiconductor manufacturing process.

11. The computer-readable storage medium of claim 8,

wherein the first pattern is a mask pattern;

wherein the design intent is a pattern that is desired to be etched on the substrate layer;

wherein the first semiconductor manufacturing process is a photolithography process; and

wherein the second semiconductor manufacturing process is an etch process.

12. The computer-readable storage medium of claim 8, wherein determining the second indicator includes determining if the second pattern is realizable using the first manufacturing process.

13. The computer-readable storage medium of claim 8, wherein determining the second indicator includes determining a process window at an evaluation point in the second pattern.

14. The computer-readable storage medium of claim 13, wherein determining the process window includes convolving the second pattern with a first manufacturing sensitivity model, which models the sensitivity of the first semiconductor manufacturing process to process variations.

15. An apparatus for determining if a pattern is robustly manufacturable, the apparatus comprising:

a receiving mechanism configured to receive a first pattern and a design intent, wherein the first pattern is intended to generate the design intent;

a first determining mechanism configured to determine a second pattern using the design intent, wherein subjecting the second pattern to a second manufacturing process is expected to generate a third pattern that is substantially similar to the design intent;

a second determining mechanism configured to determine a second indicator which indicates whether the second pattern is robustly manufacturable by a first semiconductor manufacturing process; and

a generating mechanism configured to use the second indicator to generate a first indicator that indicates whether the first pattern is robustly manufacturable.

16. The apparatus of claim 15, wherein the first pattern is intended to generate the design intent by:

subjecting the first pattern to the first semiconductor manufacturing process to obtain an intermediate pattern; and

subjecting the intermediate pattern to the second semiconductor manufacturing process to obtain a fourth pattern that is substantially similar to the design intent.

17. The apparatus of claim 15, wherein the first determining mechanism is configured to apply a second inverse-process-model to the design intent, wherein the second inverse-process-model models the inverse of the effect of the second semiconductor manufacturing process.

18. The apparatus of claim 15,

wherein the first pattern is a mask pattern;

wherein the design intent is a pattern that is desired to be etched on the substrate layer;

wherein the first semiconductor manufacturing process is a photolithography process; and

wherein the second semiconductor manufacturing process is an etch process.

19. The apparatus of claim 15, wherein the second determining mechanism is configured to determine if the second pattern is realizable using the first manufacturing process.

20. The apparatus of claim 15, wherein the second determining mechanism is configured to convolve the second pattern with a first manufacturing sensitivity model, which models the sensitivity of the first semiconductor manufacturing process to process variations.