Thin film transistor substrate and fabricating method thereof

• US 20070164289A1
• Filed: 06/30/2006
• Published: 07/19/2007
• Est. Priority Date: 12/30/2005
• Status: Active Grant

• Current Assignee: LG Display Co., Ltd.
• Original Assignee: LG Philips LCD Company Limited (LG Display Co., Ltd.)
• Inventors: Jung, Ji
• Granted Patent: US 7,777,855 B2
• Time in Patent Office: Days
• US Class Current: 257/72
• CPC Class Codes: G02F 1/136204 Arrangements to prevent high voltage or static electricity failures
• CPC Class Codes: G09G 3/006 Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays testing individual LED's G01R31/2635; testing lamps G01R31/44; testing of optical features of LCD displays G02F1/1309
• CPC Class Codes: G09G 3/3648 using an active matrix G09G3/367 - G09G3/3696 take precedence
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask

Abstract

A thin film transistor substrate and a fabricating method that includes an opening hole that separates a gate shorting line connected to a gate shorting bar used upon a lighting-inspecting of a gate line into an odd and an even gate shorting line is provided.

Claims

1. A thin film transistor substrate, comprising:

gate lines formed on a substrate;

data lines intersect the gate lines with a gate insulating film therebetween;

a thin film transistor formed at the intersection of the gate lines and the data lines;

a protective film that covers a thin film transistor formed on the gate insulating film;

a pixel electrode that is connected, via a contact hole that passes through the protective film, to the thin film transistor;

a gate shorting bar connected to an odd and an even gate;

shorting line that extends from a gate pad connected to the gate line; and

an open hole that separates at least one of the odd and the even gate shorting lines from the gate shorting bar.

2. The thin film transistor substrate as claimed in claim 1, further comprising:

a data shorting bar connected to the odd and an even data shorting line extended from a data pad connected to the data line.

3. The thin film transistor substrate as claimed in claim 1, wherein the gate shorting bar includes a first gate shorting bar connected to the odd gate shorting line;

and

a second gate shorting bar connected to the even gate shorting line,

wherein the even gate shorting line is separated from first gate shorting bar by the open hole.

wherein the second gate shorting bar is electrically connected, via a contact hole formed on a protective film, to the even gate shorting line.

4. The thin film transistor substrate as claimed in claim 3,

wherein the first gate shorting bar, and the odd and even gate shorting lines are formed with the gate lines, and

wherein the first gate shorting bar and the odd and even gate shorting lines are formed to cross each other.

5. The thin film transistor substrate as claimed in claim 3,

wherein the second gate shorting bar is formed with the data lines and crosses the gate shorting lines with the gate insulating film therebetween.

6. The thin film transistor substrate as claimed in claim 1, wherein the protective film includes:

a first contact hole that passes through the protective film to contact the drain electrode of the thin film transistor with the pixel electrode;

a second contact hole that passes through the protective film and the gate insulating film to contact a lower electrode of the gate pad with an upper electrode;

a third contact hole that passes through the protective film to contact a lower electrode of the data pad with an upper electrode; and

a fourth contact hole that passes through the protective film and the gate insulating film to contact a second gate shorting bar with the separated gate shorting line.

7. The thin film transistor substrate as claimed in claim 1, wherein the open hole is formed by a photolithography process using a mask.

23. The thin film transistor substrate as claimed in claim 4, wherein the first gate shorting bar and the odd and even gate shorting lines are formed of the same metal as the gate lines.

8. A method of fabricating a thin film transistor substrate, comprising:

forming gate lines on a substrate;

forming data lines that cross the gate lines with a gate insulating film therebetween;

forming a thin film transistor at an intersection of the gate line and the data lines;

forming a protective film that covers a thin film transistor formed on a gate insulating film;

forming a pixel electrode connected, via a contact hole that passes through the protective film, to the thin film transistor;

forming gate shorting bar connected to an odd and an even gate shorting line extended from a gate pad connected to the gate line; and

forming an open hole that separates either the odd or even gate shorting line from the gate shorting bar.

9. The method as claimed in claim 8, further comprising;

forming a data shorting bar connected to an odd and an even data shorting line extended from a data pad connected to the data line.

10. The method as claimed in claim 8, wherein forming the gate shorting bar includes:

forming a first gate shorting bar connected to the odd gate shorting line; and

forming a second gate shorting bar connected to the even gate shorting line separated from the first gate shorting bar by an open hole,

wherein the second gate shorting bar is electrically connected, via a contact hole formed on a protective film, to the even gate shorting lines.

11. The method as claimed in claim 10, wherein the first gate shorting bar and the odd and even shorting lines are formed with the gate lines, and

wherein the first gate shorting bar and odd and even shorting lines cross each other.

12. The method as claimed in claim 8, wherein said second shorting bar is formed with the data lines and is formed to cross with the gate shorting lines with the gate insulating film therebetween.

13. The method as claimed in claim 8, wherein forming the protective film includes:

forming a first contact hole that passes through the protective film to contact the drain electrode of the thin film transistor with the pixel electrode;

forming a second contact hole that passes through the protective film and the gate insulating film to contact a lower electrode of the gate pad with an upper electrode;

forming a third contact hole that passes through the protective film to contact a lower electrode of the data pad with an upper electrode; and

forming a fourth contact hole that passes through the protective film and the gate insulating film to contact a second shorting bar with the shorted gate shorting line.

14. The method as claimed in claim 8, wherein the open hole is formed by a photolithography process using a mask.

24. The method as claimed in claim 11, wherein the first gate shorting bar and the odd and even shorting lines are formed with the same metal as the gate lines.

15. A method of fabricating a thin film transistor substrate, comprising:

forming a first conductive pattern that includes gate lines, a gate electrode connected to the gate lines and a first gate shorting bar connected to the odd gate shorting line among the gate shorting lines extended from a lower gate pad electrode connected to the gate line on a substrate.

forming a gate insulating film on a substrate provided with the first conductive pattern;

forming a semiconductor layer that includes a channel and a second conductive pattern including data lines, a source/drain pattern connected to the data lines, a data shorting bar connected to a data shorting line that extends from a lower data pad connected to the data line and a second gate shorting bar connected to the even gate shorting lines that extends from the lower gate pad electrode on the gate insulating film;

forming a protective film on a gate insulating film provided with the semiconductor layer and the second conductive pattern;

forming a contact hole that exposes the drain electrode, the lower gate pad electrode, the lower data pad electrode and the even gate shorting lines and open hole area that separates the even gate shorting lines from the first gate shorting bar on the protective film; and

after a transparent conductive layer is entirely formed on the protective film, forming an open hole that separates the even gate shorting lines, a semiconductor pattern that includes a channel and a third conductive pattern including a source electrode connected to the data lines, a drain electrode opposed to a source electrode having the channel therebetween, a pixel electrode connected to the drain electrode, an upper gate pad electrode and an upper data pad electrode.

16. The method as claimed in claim 15, wherein forming the first conductive pattern includes:

disposing a gate metal layer on the substrate;

forming a photo-resist on the gate metal layer, and then forming a photo-resist pattern that exposes the gate metal layer by a first mask process;

etching the gate metal layer exposed by the photo-resist pattern to form the first conductive pattern; and

stripping a photo-resist pattern left on the first conductive pattern.

17. The method as claimed in claim 15, wherein forming the semiconductor pattern and the second conductive pattern includes:

disposing an amorphous silicon layer and an amorphous silicon layer doped with an n⁺ impurity to form a semiconductor layer for forming a channel on a substrate;

disposing a data metal layer on the semiconductor layer, and then forming a photo-resist;

forming a photo-resist pattern that exposes the data metal layer by a second mask process;

etching a data metal layer exposed by the photo-resist pattern to form the second conductive pattern; and

stripping a photo-resist pattern left on the second conductive pattern.

18. The method as claimed in claim 15, wherein forming a contact hole and an open hole area on the protective film includes:

forming a protective film on the gate insulating film, and then forming a first contact hole that passes through the protective film to expose a drain electrode via a third mask process;

forming a second contact hole that passes through the protective film and the gate insulating film to expose a lower gate pad electrode;

forming a third contact hole that passes through the protective film to expose a lower data pad electrode;

forming a fourth contact hole that passes through the protective film and the gate insulating film to expose the even gate shorting line; and

forming an area for open hole that passes through the protective film and the gate insulating film to short the even gate shorting lines from a first gate shorting bar.

19. The method as claimed in claim 15, wherein forming the open hole, the semiconductor pattern and the third conductive pattern includes:

forming a transparent conductive layer on a protective film provided with the contact hole and the open hole area;

forming a photo-resist on the transparent conductive layer, and then forming a photo-resist pattern that exposes a transparent conductive layer at a channel area and an open hole area by a fourth mask process;

etching the exposed transparent conductive layer to expose a protective film provided at a channel area and even shorting lines, and removing a transparent conductive layer of an open hole area;

etching the exposed protective film and the even shorting lines to expose a source/drain pattern, and forming an open hole that separates the even gate shorting lines exposed at the open hole area;

etching the exposed source/drain pattern to form a source and a drain electrode connected to the data lines, and then etching the semiconductor pattern to form a channel between the source and drain electrodes;

etching a transparent conductive layer exposed by an ashing process about the photo-resist pattern to form a pixel electrode, an upper gate pad electrode, an upper data pad electrode and a conductive pattern ITO that connects a second gate shorting bar to even gate shorting lines; and

stripping a photo-resist pattern left at the transparent conductive layer.

20. The method as claimed in claim 19, further includes:

forming a channel between the source electrode and the drain electrode, and then forming a channel protective film on the channel by a designated plasma process.

21. The method as claimed in claim 19, wherein the transparent conductive layer formed at the channel area of the thin film transistor and the open hole area are removed by an etching process using an OZ Acid.

22. The method as claimed in claim 19, wherein the even gate shorting lines exposed by the open hole are removed by an etching process using a mixed acid shower.