Thin film transistor substrate and fabricating method thereof
First Claim
Patent Images
1. A thin film transistor substrate, comprising:
- gate lines formed on a substrate;
data lines intersect the gate lines with a gate insulating film therebetween;
a thin film transistor formed at the intersection of the gate lines and the data lines;
a protective film that covers a thin film transistor formed on the gate insulating film;
a pixel electrode that is connected, via a contact hole that passes through the protective film, to the thin film transistor;
a gate shorting bar connected to an odd and an even gate;
shorting line that extends from a gate pad connected to the gate line; and
an open hole that separates at least one of the odd and the even gate shorting lines from the gate shorting bar.
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Abstract
A thin film transistor substrate and a fabricating method that includes an opening hole that separates a gate shorting line connected to a gate shorting bar used upon a lighting-inspecting of a gate line into an odd and an even gate shorting line is provided.
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Citations
24 Claims
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1. A thin film transistor substrate, comprising:
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gate lines formed on a substrate;
data lines intersect the gate lines with a gate insulating film therebetween;
a thin film transistor formed at the intersection of the gate lines and the data lines;
a protective film that covers a thin film transistor formed on the gate insulating film;
a pixel electrode that is connected, via a contact hole that passes through the protective film, to the thin film transistor;
a gate shorting bar connected to an odd and an even gate;
shorting line that extends from a gate pad connected to the gate line; and
an open hole that separates at least one of the odd and the even gate shorting lines from the gate shorting bar. - View Dependent Claims (2, 3, 4, 5, 6, 7, 23)
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8. A method of fabricating a thin film transistor substrate, comprising:
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forming gate lines on a substrate;
forming data lines that cross the gate lines with a gate insulating film therebetween;
forming a thin film transistor at an intersection of the gate line and the data lines;
forming a protective film that covers a thin film transistor formed on a gate insulating film;
forming a pixel electrode connected, via a contact hole that passes through the protective film, to the thin film transistor;
forming gate shorting bar connected to an odd and an even gate shorting line extended from a gate pad connected to the gate line; and
forming an open hole that separates either the odd or even gate shorting line from the gate shorting bar. - View Dependent Claims (9, 10, 11, 12, 13, 14, 24)
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15. A method of fabricating a thin film transistor substrate, comprising:
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forming a first conductive pattern that includes gate lines, a gate electrode connected to the gate lines and a first gate shorting bar connected to the odd gate shorting line among the gate shorting lines extended from a lower gate pad electrode connected to the gate line on a substrate. forming a gate insulating film on a substrate provided with the first conductive pattern;
forming a semiconductor layer that includes a channel and a second conductive pattern including data lines, a source/drain pattern connected to the data lines, a data shorting bar connected to a data shorting line that extends from a lower data pad connected to the data line and a second gate shorting bar connected to the even gate shorting lines that extends from the lower gate pad electrode on the gate insulating film;
forming a protective film on a gate insulating film provided with the semiconductor layer and the second conductive pattern;
forming a contact hole that exposes the drain electrode, the lower gate pad electrode, the lower data pad electrode and the even gate shorting lines and open hole area that separates the even gate shorting lines from the first gate shorting bar on the protective film; and
after a transparent conductive layer is entirely formed on the protective film, forming an open hole that separates the even gate shorting lines, a semiconductor pattern that includes a channel and a third conductive pattern including a source electrode connected to the data lines, a drain electrode opposed to a source electrode having the channel therebetween, a pixel electrode connected to the drain electrode, an upper gate pad electrode and an upper data pad electrode. - View Dependent Claims (16, 17, 18, 19, 20, 21, 22)
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Specification