Semiconductor device and manufacturing method thereof

• US 20070164339A1
• Filed: 03/08/2006
• Published: 07/19/2007
• Est. Priority Date: 11/25/2005
• Status: Active Grant

• Current Assignee: Fujitsu Semiconductor Limited (Fujitsu Limited), Quantum Color Graphics Incorporated
• Original Assignee: Fujitsu Limited
• Inventors: Suzuki, Yoshiyuki, Asano, Masayoshi
• Granted Patent: US 7,772,634 B2
• Time in Patent Office: Days
• US Class Current: 257/296
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H01L 29/94 Metal-insulator-semiconductors, e.g. MOS
• CPC Class Codes: H10B 12/03 Making the capacitor or connections thereto
• CPC Class Codes: H10B 12/05 Making the transistor
• CPC Class Codes: H10B 12/30 DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells

Abstract

A channel stop region is formed immediately under an STI, and thereafter, an ion implantation is performed with conditions in which an impurity is doped into an upper layer portion of an active region, and at the same time, the impurity is also doped into immediately under another STI, and a channel dose region is formed at the upper layer portion of the active region, and another channel stop region is formed immediately under the STI.

Claims

1. A semiconductor device which includes a semiconductor substrate, and plural element isolation structures defining active regions on the semiconductor substrate and constituted by trenches respectively formed at plural element isolation regions of the semiconductor substrate, and inside of the respective trenches are filled with insulators,

wherein the plural element isolation structures are composed of a first element isolation structure in which the insulator inside of the trench is thick and a second element isolation structure in which the insulator is thinner than the first element isolation structure, the semiconductor device comprising:

a first impurity region at least formed at a lower portion of the first element isolation structure in the semiconductor substrate;

a second impurity region formed at a matched portion under the second element isolation structure in the semiconductor substrate, and deeper than said first impurity region;

a third impurity region formed at a surface layer portion of the active region; and

a fourth impurity region formed at a matched portion under the second element isolation structure in the semiconductor substrate, and between the second element isolation structure and said second impurity region.

2. The semiconductor device according to claim 1,

wherein said first impurity region, said second impurity region, said third impurity region, and said fourth impurity region are constituted by doping impurities having same conductivity type.

3. The semiconductor device according to claim 1,

wherein said first impurity region and said second impurity region are formed to be same impurity concentration.

4. The semiconductor device according to claim 1,

wherein said third impurity region and said fourth impurity region are formed to be same impurity concentration.

5. The semiconductor device according to claim 4,

wherein the impurity concentration of said fourth impurity region is 1×

10¹⁷/cm³ or more.

6. The semiconductor device according to claim 1, further comprising:

a transistor structure formed at the active region; and

a pair of capacitor structures formed to straddle a pair of active regions adjacent via the second element isolation structure, and constituted by electrically isolated from one another by the insulator of the second element isolation structure.

7. A manufacturing method of a semiconductor device, comprising the steps of:

forming trenches at plural element isolation regions of a semiconductor substrate respectively, and filling inside of the respective trenches with insulators;

defining active regions on the semiconductor substrate by forming a first element isolation structure in a first trench and a second element isolation structure in a second trench respectively by removing a part of the insulator only from inside of the second trench, in which the formed respective trenches are the first trench or the second trench;

simultaneously forming a first impurity region at least at a lower portion of the first element isolation structure and a second impurity region at a matched portion under the second element isolation structure and deeper than the first impurity region by doping a first impurity into a portion including the first element isolation structure and the second element isolation structure of the semiconductor substrate; and

simultaneously forming a third impurity region at a surface layer portion of the active region and a fourth impurity region at a matched portion under the second element isolation structure and between the second element isolation structure and the second impurity region by doping a second impurity into a portion including the first element isolation structure and the second element isolation structure of the semiconductor substrate.

8. The manufacturing method of the semiconductor device according to claim 7,

wherein a doping condition of the second impurity is adjusted so that an impurity concentration of the fourth impurity region becomes to be the impurity concentration of the second impurity region or more.

9. The manufacturing method of the semiconductor device according to claim 7,

wherein the first impurity and the second impurity are same conductivity type.

10. The manufacturing method of the semiconductor device according to claim 8,

wherein the impurity concentration of the fourth impurity region is 1×

10¹⁷/cm³ or more.

11. The manufacturing method of the semiconductor device according to claim 8,

wherein the first impurity region and the second impurity region are integrally formed in a shape extending from the first element isolation structure to the second element isolation structure, and being deep at a matched portion under the second element isolation structure.

12. The manufacturing method of the semiconductor device according to claim 8,

wherein a transistor structure is formed at the active region, and a pair of capacitor structures are formed so as to straddle between a pair of the active regions adjacent via the second element isolation structure and constituted by electrically isolated from one another by the insulator of the second element isolation structure.

13. The manufacturing method of the semiconductor device according to claim 12, further comprising the steps of:

forming an insulating film from the active region to a sidewall of the trench of the second element isolation structure after the third impurity region and the fourth impurity region are formed;

forming a conductive film on the insulating film; and

simultaneously forming a gate electrode of the transistor structure interposing the insulating film functioning as a gate insulating film on the active region, and an upper electrode of the capacitor structure interposing the insulating film functioning as a dielectric film on the pair of the active regions adjacent via the second element isolation structure, by processing the conductive film.

14. The manufacturing method of the semiconductor device according to claim 13,

wherein a pair of fifth impurity regions are formed by doping a third impurity into a surface layer of the active regions at both sides of the gate electrode by using the gate electrode and the upper electrode as masks, and the third impurity is doped into inside of the gate electrode and inside of the upper electrode.