SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

• US 20070164351A1
• Filed: 11/20/2006
• Published: 07/19/2007
• Est. Priority Date: 01/17/2006
• Status: Abandoned Application

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: HAMAMOTO, Takeshi
• Application Number:
  US11/561,580
• Publication Number:
  US 20070164351A1
• Time in Patent Office: Days
• US Class Current: 257/324
• CPC Class Codes: H01L 29/7841 with floating body, e.g. programmable transistors
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 12/20 DRAM devices comprising floating-body transistors, e.g. floating-body cells

Abstract

A semiconductor device of one embodiment of the present invention includes a substrate; isolation layers, each of which is formed in a trench formed on the substrate and has an insulating film and a conductive layer; a semiconductor layer of a first conductivity type for storing signal charges, formed between the isolation layers and isolated from the conductive layers by the insulating films; a semiconductor layer of a second conductivity type, formed under the semiconductor layer of the first conductivity type; and a transistor having a gate insulator film formed on the semiconductor layer of the first conductivity type and a gate electrode formed on the gate insulator film.

Claims

1. A semiconductor device, comprising:

a substrate;

isolation layers, each of which is formed in a trench formed on the substrate and has an insulating film and a conductive layer;

a semiconductor layer of a first conductivity type for storing signal charges, formed between the isolation layers and isolated from the conductive layers by the insulating films;

a semiconductor layer of a second conductivity type, formed under the semiconductor layer of the first conductivity type; and

a transistor having a gate insulator film formed on the semiconductor layer of the first conductivity type and a gate electrode formed on the gate insulator film.

2. The semiconductor device according to claim 1, wherein the conductive layer is electrically insulated from the substrate.

3. The semiconductor device according to claim 2, wherein the insulating film constitutes the sides and bottom surface of the isolation layer.

4. The semiconductor device according to claim 2, wherein the conductive layer is connected to fixed potential.

5. The semiconductor device according to claim 1, wherein the conductive layer is electrically connected to the substrate.

6. The semiconductor device according to claim 5, wherein the insulating film constitutes the sides of the isolation layer, and the conductive layer constitutes the bottom surface of the isolation layer.

7. The semiconductor device according to claim 1, wherein the insulating film constitutes an outer envelope of the isolation layer, and the conductive layer constitutes a core portion of the isolation layer.

8. The semiconductor device according to claim 1, wherein the insulating film intervenes between the conductive layer and the semiconductor layer of the first conductivity type and isolates the conductive layer from the semiconductor layer of the first conductivity type.

9. The semiconductor device according to claim 1, wherein the conductive layer is opposite through the insulating film to the semiconductor layer of the first conductivity type and isolated from the semiconductor layer of the first conductivity type by the insulating film.

10. The semiconductor device according to claim 1, wherein the insulating film is formed of a silicon oxide film, and the conductive layer is formed of polycrystalline silicon.

11. The semiconductor device according to claim 1, wherein the semiconductor layer of the first conductivity type is a p-type well, and the semiconductor layer of the second conductivity type is an n-type well.

12. The semiconductor device according to claim 1, wherein the substrate is a bulk substrate.

13. The semiconductor device according to claim 1, wherein the transistor is a transistor constituting a capacitorless memory cell.

14. A method for manufacturing a semiconductor device, comprising:

forming trenches for isolation, on a substrate;

forming isolation layers, each of which has an insulating film and a conductive layer, in the trenches;

forming a semiconductor layer of a first conductivity type for storing signal charges between the isolation layers so that the semiconductor layer of the first conductivity type is isolated from the conductive layers by the insulating films;

forming a semiconductor layer of a second conductivity type under the semiconductor layer of the first conductivity type; and

forming a transistor having a gate insulator film formed on the semiconductor layer of the first conductivity type and a gate electrode formed on the gate insulator film.

15. The method for manufacturing a semiconductor device according to claim 14, forming each of the isolation layers, by forming the insulating film and then forming the conductive layer so that the conductive layer is electrically insulated from the substrate.

16. The method for manufacturing a semiconductor device according to claim 15, forming each of the isolation layers, by forming the insulating film on the sides and bottom surface of the trench and then filling in the trench with the conductive layer.

17. The method for manufacturing a semiconductor device according to claim 14, forming each of the isolation layers, by forming the insulating film, then removing a portion of the insulating film and then forming the conductive layer so that the conductive layer is electrically connected to the substrate.

18. The method for manufacturing a semiconductor device according to claim 17, forming each of the isolation layers, by forming the insulating film on the sides and bottom surface of the trench, then removing a portion or the entirety of the insulating film formed on the bottom surface of the trench and then filling in the trench with the conductive layer.

19. The method for manufacturing a semiconductor device according to claim 14, wherein the substrate is a bulk substrate.

20. The method for manufacturing a semiconductor device according to claim 14, wherein the transistor is a transistor constituting a capacitorless memory cell.