MULTI-BIT-PER-CELL NVM STRUCTURES AND ARCHITECTURE

• US 20070164352A1
• Filed: 12/12/2006
• Published: 07/19/2007
• Est. Priority Date: 12/12/2005
• Status: Abandoned Application

• Current Assignee: Regents of the University of California (University of California)
• Original Assignee: Regents of the University of California (University of California)
• Inventors: King, Tsu-Jae, Padilla, Alvaro
• Application Number:
  US11/609,846
• Publication Number:
  US 20070164352A1
• Time in Patent Office: Days
• US Class Current: 257/324
• CPC Class Codes: G11C 11/5671 using charge trapping in an insulator
• CPC Class Codes: G11C 16/0475 comprising two or more independent storage sites which store independent data
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/0491 Virtual ground arrays
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7887 Programmable transistors with more than two possible different levels of programmation
• CPC Class Codes: H01L 29/7923 Programmable transistors with more than two possible different levels of programmation
• CPC Class Codes: H10B 41/10 characterised by the top-view layout
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 43/10 characterised by the top-view layout
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A transistor structure, such as a Double-gated FET (DG FET), that has been modified to include a charge-trapping region used to store either 2- or 4-bits of information. The charge-trapping region can, for example, be embedded in the gate dielectric stack underneath each gate electrode, or placed on the sidewalls of each gate electrode.

Claims

1. An apparatus, comprising:

a transistor structure;

said transistor structure having at least one gate electrode;

said transistor structure having at least one charge-trapping region configured to store a bit of information;

wherein off-state current is utilized to distinguish charge state of said bit in said transistor structure.

2. An apparatus as recited in claim 1:

wherein a bit state in the transistor structure is determined by off-state current; and

wherein a change in off-state current is utilized to determine a change in charge state of a bit in the charge-trapping region.

3. An apparatus as recited in claim 1, wherein a change in the off-state current arises from a change in transverse electric field due to stored charge.

4. An apparatus as recited in claim 1, wherein said transistor structure has one or more charge-trapping regions configured for storing 2 bits of information.

5. An apparatus as recited in claim 4, wherein said transistor structure comprises a single-gate transistor structure.

6. An apparatus as recited in claim 5:

wherein said single-gate has a pair of sidewalls; and

wherein charge-trapping regions are located along each of said sidewalls.

7. An apparatus as recited in claim 1, wherein said at least one charge-trapping region is configured for storing 4 bits of information.

8. An apparatus as recited in claim 7, wherein said transistor structure comprises a plurality of gate electrodes.

9. An apparatus as recited in claim 8:

wherein said at least one charge-trapping region is embedded in a gate dielectric stack underneath each gate electrode.

10. An apparatus as recited in claim 8:

wherein each gate electrode has a pair of sidewalls; and

wherein charge-trapping regions are located along each of said sidewalls of each gate electrode.

11. An apparatus as recited in claim 8, wherein said transistor structure includes symmetric double gates.

12. An apparatus as recited in claim 8, wherein said transistor structure includes asymmetric double gates.

13. An apparatus as recited in claim 8:

wherein said transistor structure comprises an undoped or lightly doped silicon film with thickness T_si; and

wherein said double-gates have gate-length L_g.

14. An apparatus as recited in claim 8:

wherein said transistor structure includes an oxide layer underneath each charge-trapping region; and

wherein said oxide layer has a thickness sufficiently thin to allow for tunneling of electrons or holes from the silicon film into the charge-trapping region or from the charge-trapping region into the silicon film at relatively low voltages.

15. An apparatus, comprising:

a transistor structure;

said transistor structure having at least one gate electrode;

said transistor structure having at least one charge-trapping region;

wherein the at least one gate electrode and the at least one charge-trapping region are configured for storing 2 bits of information;

wherein off-state current is utilized to distinguish charge state of said bit in said transistor structure.

16. An apparatus as recited in claim 15:

wherein a bit state in the transistor structure is determined by off-state current; and

wherein a change in off-state current is utilized to determine a change in charge state of a bit in the charge-trapping region.

17. An apparatus as recited in claim 15, wherein a change in the off-state current arises from a change in transverse electric field due to stored charge.

18. An apparatus as recited in claim 15, wherein said transistor structure comprises a single-gate transistor structure.

19. An apparatus as recited in claim 15:

wherein each gate electrode has a pair of sidewalls; and

wherein a charge-trapping region is located along each of said sidewalls.

20. An apparatus, comprising:

a transistor structure;

said transistor structure having at least one gate electrode;

said transistor structure having at least one charge-trapping region;

wherein said at least one gate electrode and said at least one charge-trapping region are configured for storing 4 bits of information; and

wherein off-state current is utilized to distinguish charge state of said bit in said transistor structure.

21. An apparatus as recited in claim 20:

wherein a bit state in the transistor structure is determined by the transistor off-state current; and

wherein a change in off-state current is utilized to determine a change in charge state of a bit in the charge-trapping region.

22. An apparatus as recited in claim 20, wherein a change in the off-state current arises from a change in transverse electric field due to stored charge.

23. An apparatus as recited in claim 20, wherein said transistor structure comprises a plurality of gate electrodes.

24. An apparatus as recited in claim 23:

wherein said at least one charge-trapping region is embedded in a dielectric stack underneath each gate electrode.

25. An apparatus as recited in claim 23:

wherein each gate electrode has sidewalls; and

wherein said at least one charge-trapping region is embedded along each of said sidewalls.

26. An apparatus as recited in claim 23, wherein said transistor structure includes symmetric double gates.

27. An apparatus as recited in claim 23, wherein said transistor structure includes asymmetric double gates.

28. An apparatus as recited in claim 23:

wherein said transistor structure comprises an undoped or lightly doped silicon film with thickness T_si; and

wherein said gate electrodes have gate-length L_g.

29. An apparatus as recited in claim 23:

wherein said transistor structure includes an oxide layer underneath each charge-trapping region; and

wherein said oxide layer has a thickness sufficiently thin to allow for tunneling of electrons or holes from the silicon film into the charge-trapping region or from the charge-trapping region into the silicon film at relatively low operating voltages.

30. An apparatus, comprising:

a transistor structure;

said transistor structure having at least one charge-trapping region;

wherein said transistor structure has a plurality of gate electrodes;

wherein said at least one charge-trapping region and said plurality of gate electrodes are configured for storing 4 bits of information; and

wherein off-state current is utilized to distinguish charge state of said bit in said transistor structure.

31. An apparatus as recited in claim 30:

wherein a bit state in the transistor structure is determined by off-state current; and

wherein a change in off-state current is utilized to determine a change in charge state of a bit in the charge-trapping region.

32. An apparatus as recited in claim 30, wherein a change in the off-state current arises from a change in transverse electric field due to stored charge.

33. An apparatus as recited in claim 30, wherein said transistor structure comprises a gate dielectric stack underneath each gate electrode.

34. An apparatus as recited in claim 33:

wherein said at least one charge-trapping region is embedded in said gate dielectric stack underneath each gate electrode.

35. An apparatus as recited in claim 30:

wherein each gate electrode has a pair of sidewalls; and

wherein said at least one charge-trapping region is located along each of said sidewalls of each gate electrode.

36. An apparatus as recited in claim 30, wherein said transistor structure includes symmetric double gates.

37. An apparatus as recited in claim 30, wherein said transistor structure includes asymmetric double gates.

38. An apparatus as recited in claim 30:

wherein said transistor structure comprises an undoped or lightly doped silicon film with thickness T_si; and

wherein said gate electrodes have gate-length L_g.

39. An apparatus as recited in claim 30:

wherein said transistor structure includes an oxide layer underneath each charge-trapping region; and

wherein said oxide layer has a thickness sufficiently thin to allow for tunneling of electrons or holes from the silicon film into the charge-trapping region or from the charge-trapping region into the silicon film at relatively low operating voltages.