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MULTI-BIT-PER-CELL NVM STRUCTURES AND ARCHITECTURE

  • US 20070164352A1
  • Filed: 12/12/2006
  • Published: 07/19/2007
  • Est. Priority Date: 12/12/2005
  • Status: Abandoned Application
First Claim
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1. An apparatus, comprising:

  • a transistor structure;

    said transistor structure having at least one gate electrode;

    said transistor structure having at least one charge-trapping region configured to store a bit of information;

    wherein off-state current is utilized to distinguish charge state of said bit in said transistor structure.

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