Semiconductor device and fabricating method thereof

• US 20070164370A1
• Filed: 01/18/2006
• Published: 07/19/2007
• Est. Priority Date: 01/18/2006
• Status: Active Grant

• Current Assignee: Macronix International Co., Ltd.
• Original Assignee: Macronix International Co., Ltd.
• Inventors: Chen, Kuan-Po, Liu, Mu-Yi
• Granted Patent: US 8,729,635 B2
• Time in Patent Office: Days
• US Class Current: 257/382
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/7842 means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate variation of the composition of the channel H01L29/1054
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors

Abstract

A semiconductor device is provided. The semiconductor device comprises a substrate, a stacked gate structure, doped regions and high stress material layers. The stacked gate structure is located on the substrate. The stacked gate structure includes at least a dielectric layer and a gate sequentially disposed over the substrate. The doped regions are disposed in the substrate on each side of the stacked gate structure. The high stress material layers are disposed on the substrate to cover the doped regions. The high stress material layers can increase the mobility of the carriers in the doped regions and hence accelerate the operating speed of the device.

Claims

1. A semiconductor device, comprising:

a substrate;

a stacked gate structure disposed on the substrate, wherein the stacked gate structure comprises at least a dielectric layer and a gate sequentially stacked over the substrate;

a doped region disposed on the respective sides of the stacked gate structure; and

a high stress material layer disposed on the doped region.

2. The semiconductor device of claim 1, wherein the high stress material with a stress is higher than −

7.28e7 (dynes/cmˆ

2).

3. The semiconductor device of claim 2, wherein the high stress material with a stress is preferable within a range of 1.53e7 (dynes/cmˆ

2) and 2.71e9 (dynes/cmˆ

2).

4. The semiconductor device of claim 1, wherein the high stress material layer is fabricated using a material comprising at least nitrogen and silicon, wherein the high stress material with a thickness is higher than half of that of the stacked gate structure.

5. The semiconductor device of claim 2, wherein the material constituting the high stress material layer is selected from a group consisting of silicon nitride, silicon oxynitride, silicon oxide or a combination of the above materials.

6. The semiconductor device of claim 4, wherein the stacked gate structure comprises the dielectric layer, a charge-storage layer, a charge barrier layer and the gate sequentially disposed over the substrate.

7. The semiconductor device of claim 5, wherein the material constituting the charge-storage layer comprises silicon nitride.

8. The semiconductor device of claim 5, wherein the material constituting the dielectric layer and the charge barrier layer comprises silicon oxide.

9. The semiconductor device of claim 4, wherein the doped region is a buried bit line.

10. A method of fabricating a semiconductor device, comprising the steps of:

providing a substrate;

forming a stacked gate structure on the substrate, wherein the stacked gate structure comprises at least a dielectric layer and a gate sequentially disposed over the substrate;

forming a doped region on the respective sides of the stacked gate structure; and

forming a high stress material layer over the doped region.

11. The method of claim 10, wherein the high stress material layer is fabricated using a material comprising at least nitrogen and silicon.

12. The method device of claim 11, wherein the material constituting the high stress material layer is selected from a group consisting of silicon nitride, silicon oxynitride, silicon oxide or a combination of the above materials.

13. The method of claim 11, wherein the step of forming the high stress material layer includes performing a chemical vapor deposition process and adjusting the ratio between the nitrogen-containing gas and the silicon-containing gas during the chemical vapor deposition process.

14. The method of claim 13, wherein the stacked gate structure comprises the dielectric layer, a charge-storage layer, a charge barrier layer and the gate sequentially stacked over the substrate.

15. The method of claim 14, wherein the material constituting the charge-storage layer comprises silicon nitride.

16. The method of claim 14, wherein the doped region is a buried bit line.