SEMICONDUCTOR WAFER SCALE PACKAGE SYSTEM
First Claim
Patent Images
1. A semiconductor wafer scale package system comprising:
- providing a semiconductor substrate having a through-hole via with a conductive coating;
forming a filled via by filling the through-hole via with a conductive material;
coupling a package substrate to the filled via; and
singulating a chip scale package from the semiconductor substrate and the package substrate.
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Abstract
A semiconductor wafer scale package system is provided including providing a semiconductor substrate having a through-hole via with a conductive coating, forming a filled via by filling the through-hole via with a conductive material, coupling a package substrate to the filled via, and singulating a chip scale package from the semiconductor substrate and the package substrate.
11 Citations
20 Claims
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1. A semiconductor wafer scale package system comprising:
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providing a semiconductor substrate having a through-hole via with a conductive coating; forming a filled via by filling the through-hole via with a conductive material; coupling a package substrate to the filled via; and singulating a chip scale package from the semiconductor substrate and the package substrate. - View Dependent Claims (2, 3, 4, 5)
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6. A semiconductor wafer scale package system comprising:
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providing a semiconductor substrate having a through-hole via lined with a conductive coating including forming the through-hole via near the edge of a semiconductor device; forming a filled via by filling the through-hole via with a conductive material including spraying or printing the conductive material; coupling a package substrate to the filled via including coupling all of the filled via on the semiconductor substrate to a package substrate; and singulating a chip scale package from the semiconductor substrate and the package substrate including singulating the chip scale package. - View Dependent Claims (7, 8, 9, 10)
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11. A semiconductor wafer scale package system comprising:
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a semiconductor substrate having a through-hole via lined with a conductive coating; a conductive material filling the through-hole via on the conductive coating; and a package substrate having a component interconnect, the component interconnect connected to the conductive material, and the package substrate having sides characteristic of being simultaneously singulated along with the semiconductor substrate being singulated from a semiconductor wafer. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20)
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Specification