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SEMICONDUCTOR WAFER SCALE PACKAGE SYSTEM

  • US 20070164422A1
  • Filed: 12/22/2006
  • Published: 07/19/2007
  • Est. Priority Date: 01/13/2006
  • Status: Active Grant
First Claim
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1. A semiconductor wafer scale package system comprising:

  • providing a semiconductor substrate having a through-hole via with a conductive coating;

    forming a filled via by filling the through-hole via with a conductive material;

    coupling a package substrate to the filled via; and

    singulating a chip scale package from the semiconductor substrate and the package substrate.

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