Feedback circuit for line load compensation and reflection reduction

• US 20070164779A1
• Filed: 12/30/2005
• Published: 07/19/2007
• Est. Priority Date: 12/30/2005
• Status: Active Grant

• Current Assignee: Honeywell International Inc.
• Original Assignee: Honeywell International Inc.
• Inventors: Weston, Lance, Mole, David, Hinkson, Richard
• Granted Patent: US 7,489,158 B2
• Time in Patent Office: Days
• US Class Current: 326/26
• CPC Class Codes: H04L 25/0272 Arrangements for coupling to multiple lines, e.g. for differential transmission
• CPC Class Codes: H04L 25/0298 Arrangement for terminating transmission lines

Abstract

Line load compensation and reflection reduction in a signal transmitting circuit is provided using feedback capacitors. The feedback capacitor serially coupled with a resistance generates an RC rise/fall time that is independent of the line load. Additionally, by selecting a capacitor that yields a rise/fall time of approximately ⅓ of the maximum bit transmission time, signal reflection on the signal line can be reduced. Accordingly, by incorporating the feedback capacitor with a differential drive circuit, such as the IB 485 driver, variations in line load can be compensated for while also reducing signal reflection due to un-terminated or improperly terminated signal lines, thus allowing a free topology implementation.

Claims

1. A feedback sub-circuit for providing line load compensation and reflection reduction in a signal transmitting circuit, said feedback sub-circuit comprising:

a feedback capacitor; and

at least one resistor in serial connection with said feedback capacitor, a rise/fall time of said feedback capacitor and said resistor being equal to a fractional value of a bit transmission time, said transmission bit time being based on a baud rate and a maximum transmission line length.

2. The feedback sub-circuit of claim 1, wherein said signal transmitting circuit is differential drive circuit.

3. The feedback sub-circuit of claim 1, wherein said fractional value is equal to 1/3 of said bit transmission time.

4. A feedback sub-circuit for providing line load compensation and reflection reduction in a signal transmitting circuit, said feedback sub-circuit comprising:

a first transistor, a second transistor and a third transistor, a first lead of said first transistor and a second lead of said second transistor being connected to a third lead of said third transistor at a first node, a third lead of said second transistor being connected to a first lead of said third transistor at a second node; and

a feedback capacitor having a first lead connected to a third lead of said first transistor at a third node, and a second lead connected to a second lead of said third transistor at a fourth node.

5. The feedback sub-circuit as in claim 4, further comprising:

a first resistor having a first lead connected to a first lead of said second transistor at a fifth node, and a second lead connected to said second node;

a voltage source having a positive lead connected to said fifth node;

a second resistor having a first lead adapted for being connected to an input signal source having an arbitrarily selected load, and a second lead of said second resistor being connected to said third lead of said first transistor at said third node;

a third resistor having a first lead connected to said third node, and a second lead connected to said fifth node;

a fourth resistor having a first lead connected to a second lead of said first transistor at a sixth node, and a second lead connected to a ground potential; and

a diode having a first lead connected to said fourth node, and a second lead adapted for emitting an output signal, said output signal being independent of the load of said input signal.

6. The feedback sub-circuit as in claim 4, further comprising an input line adapted for connecting an input signal source having an arbitrarily selected load to said base of said first transistor at said third node.

7. The feedback sub-circuit as in claim 4, wherein said first, second and third transistors are Bipolar Junction Transistors, said first lead of each transistor being an emitter, said second lead of each transistor being a collector and said third lead of each transistor being a base.

8. The feedback sub-circuit as in claim 4, wherein said first, second and third transistors are Field Effect Transistors, said first lead of each transistor being a drain, said second lead of each transistor being a source and said third lead of each transistor being a gate.

9. The feedback sub-circuit as in claim 4, wherein said feedback capacitor has a capacitance selected to produce a constant rise/fall time regardless of said load of said input signal and reduce signal reflection, said rise/fall time of said feedback capacitor being equal to fractional value of a transmission bit time of said signal transmitting circuit, said bit transmission time being based on a baud rate and a maximum transmission line length.

10. The feedback sub-circuit of claim 4, wherein said fractional value is equal to ⅓

of said transmission bit time.

11. The feedback sub-circuit as in claim 4, wherein a plurality of said feedback sub-circuits is integrated with an differential drive circuit.

12. The feedback sub-circuit as in claim 11, wherein four said feedback sub-circuits comprise said plurality of feedback sub-circuits, said four feedback sub-circuits being configured in a H-bridge configuration with two of said four feedback sub-circuits having PNP transistors and a remaining two of said four feedback sub-circuits having NPN transistors.

13. A differential drive circuit having a free topology and variable line load requirement, comprising:

a plurality of feedback sub-circuit for providing line load compensation and reflection reduction, each feedback sub-circuit of said plurality of feedback sub-circuits comprising;

a first transistor, a second transistor and a third transistor, a first lead of said first transistor and a second lead of said second transistor being connected to a third lead of said third transistor at a first node, a third lead of said second transistor being connected to a first lead of said third transistor at a second node;

a feedback capacitor having a first lead connected to a third lead of said first transistor at a third node, and a second lead connected to a second lead of said third transistor at a fourth node;

a first resistor having a first lead connected to a first lead of said second transistor at a fifth node, and a second lead connected to said second node;

a voltage source having a positive lead connected to said fifth node;

a second resistor having a first lead adapted for being connected to an input signal source having an arbitrarily selected load, and a second lead of said second resistor being connected to said third lead of said first transistor at said third node;

a third resistor having a first lead connected to said third node, and a second lead connected to said fifth node;

a fourth resistor having a first lead connected to a second lead of said first transistor at a sixth node, and a second lead connected to a ground potential; and

a diode having a first lead connected to said fourth node, and a second lead adapted for emitting an output signal, said output signal being independent of the load of said input signal.

14. The differential drive circuit as in claim 13, wherein said first, second and third transistors are Bipolar Junction Transistors, said first lead of each transistor being an emitter, said second lead of each transistor being a collector and said third lead of each transistor being a base.

15. The differential drive circuit as in claim 13, wherein said first, second and third transistors are Field Effect Transistors, said first lead of each transistor being a drain, said second lead of each transistor being a source and said third lead of each transistor being a gate.

16. The differential drive circuit as in claim 13, wherein said feedback capacitor has a capacitance selected to produce a constant rise/fall time regardless of said load of said input signal and reduce signal reflection, said rise/fall time of said feedback capacitor being equal to a fractional value of a transmission bit time of said signal transmitting circuit.

17. The differential drive circuit as in claim 13, wherein said fractional value is equal to ⅓

of said transmission bit time.

18. The differential drive circuit as in claim 13, wherein four said feedback sub-circuits comprise said plurality of feedback sub-circuits, said four feedback sub-circuits being configured in an H-bridge configuration with two of said four feedback sub-circuits having PNP transistors and a remaining two of said four feedback sub-circuits having NPN transistors.