LOW-POWER FPGA CIRCUITS AND METHODS

• US 20070164785A1
• Filed: 12/04/2006
• Published: 07/19/2007
• Est. Priority Date: 06/04/2004
• Status: Active Grant

• Current Assignee: Regents of the University of California (University of California)
• Original Assignee: Regents of the University of California (University of California)
• Inventors: HE, LEI
• Granted Patent: US 7,714,610 B2
• Time in Patent Office: Days
• US Class Current: 326/41
• CPC Class Codes: G06F 2111/06 Multi-objective optimisation, e.g. Pareto optimisation using simulated annealing [SA], ant colony algorithms or genetic algorithms [GA]
• CPC Class Codes: G06F 2119/06 Power analysis or power optimisation
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: H03K 19/17728 Reconfigurable logic blocks, e.g. lookup tables
• CPC Class Codes: H03K 19/17736 Structural details of routing resources
• CPC Class Codes: H03K 19/17784 for supply voltage

Abstract

Field Programmable Logic Arrays (FPGAs) are described which utilize multiple power supply voltages to reduce both dynamic power and leakage power without sacrificing speed or substantially increasing device area. Power reduction mechanisms are described for numerous portions of the FPGA, including logic blocks, routing circuits, connection blocks, switch blocks, configuration memory cells, and so forth. Embodiments describe circuits and methods for implementing multiple supplies as sources of V_dd, multiple voltage thresholding V_t, signal level translators, and power gating of circuitry to deactivate portions of the circuit which are inactive. The supply voltage levels can be fixed, or programmable. Methods are described for performing circuit CAD in the routing and assignment process on FPGAs, in particular for optimizing FPGA use having the power reduction circuits taught. Routing methods describe utilizing slack timing, power sensitivity, trace-based simulations, and other techniques to optimize circuit utilization on a multi V_dd FPGA.

Claims

1. An integrated circuit field programmable gate array (FPGA), comprising:

a plurality of logic blocks configured for performing combinational or sequential logic operations based on programming of said FPGA in response to one or more logic inputs;

a plurality of programmable routing channels configured for interconnecting said logic blocks for routing input signals to said logic blocks and output signals from said logic blocks based on programming of said FPGA;

a plurality of memory cells within said FPGA for configuring logic block operation and signal routing within said programmable routing channels; and

supply voltage selection means for operating said logic blocks and/or switching elements within said programmable routing channels which are either or both taken from a supply voltage V_dd selected from a plurality of discrete supply voltage levels.

2. An FPGA as recited in claim 1, wherein said supply voltage selection means comprises designing transistor geometries within the specific blocks to operate at different voltage levels, or at either voltage level, and the inclusion of level converters for shifting from lower voltage referenced signals to higher voltage referenced signals as determined during routing and configuration of the FPGA.

3. An FPGA as recited in claim 1, further comprising means for power gating of said logic blocks and switching within said programmable routing channels into an inactive powered down state in response to a configuration setting in which the logic block or switching is not in use.

4. An integrated circuit field programmable gate array (FPGA) containing an array of gates adapted for being programmed after manufacture for implementing desired electronic functionality, comprising:

logic blocks configured for performing combinational or sequential logic operations based on programming of said FPGA in response to one or more logic inputs;

said logic blocks configured for operating at a supply voltage V_dd selected from multiple discrete supply voltage levels;

programmable routing channels configured for interconnecting said logic blocks for routing input signals to said logic blocks and output signals from said logic blocks based on programming of said FPGA; and

memory cells within said FPGA for configuring logic block operation and signal routing within said programmable routing channels.

5. An FPGA as recited in claim 4, wherein said FPGA is configured with logic blocks separated as islands within a routing structure, wherein said routing channels are formed in the spaces between said logic blocks.

6. An FPGA as recited in claim 5, wherein said logic blocks with homogeneous supply voltage of high, low, or no supply voltage, are arranged in a row-based or interleaved layout pattern within said routing structure.

7. An FPGA as recited in claim 4, wherein said programmable routing channels comprises:

a plurality of wire segments surrounding said logic blocks;

a plurality of connection blocks configured for connecting the inputs and outputs of said logic block with said wire segments; and

a plurality of switch blocks at the intersection of wire segments for controlling the path of signal routing between sets of wire segments.

8. An FPGA as recited in claim 7, further comprising circuitry within said connection block or routing switch for selecting one of multiple discrete supply voltage levels as V_dd for operating said connection block or routing switch.

9. An FPGA as recited in claim 8, further comprising:

a decoder within said routing switch configured for controlling routing switch state patterns in response to a binary input value;

wherein the number of configuration bits needed to set the state of the routing switches is reduced and fewer memory cells are necessary for controlling the state of said routing switch; and

power gating circuits to switch off power to the decoder when the routing switch is not in use.

10. An FPGA as recited in claim 7, further comprising:

power gating circuitry within said connection block for switching off power to any output buffer which is not selected according to the configuration programmed in said memory cells; and

wherein power gating is performed without the need of additional memory cells.

11. An FPGA as recited in claim 7, further comprising:

power gating circuitry within said switch block for switching off power to switching elements within said switch block that are not configured in response to configuration programming within said memory cells for switching signals between said wire segments; and

wherein power gating circuitry powers down the associated elements without the need of additional memory cells.

12. An FPGA as recited in claim 4, wherein said programmable routing is configured with multiple tracks for routing signals referenced to at least a portion of said multiple discrete supply voltage levels.

13. An FPGA as recited in claim 4:

wherein said programmable routing is configured to route signals referenced to a single supply voltage V_dd; and

further comprising level translators coupled within logic blocks operating from other of the multiple discrete supply voltage levels.

14. An FPGA as recited in claim 13, wherein said programmable routing routes signals referenced to the highest supply voltage V_dd within the set of multiple discrete supply voltage levels or fixed voltage level, used with.

15. An FPGA as recited in claim 14, wherein said multiple discrete supply voltage levels comprises a low V_dd(V_ddL) and a high V_dd(V_ddH).

16. An FPGA as recited in claim 4, further comprising a power supply configured for supplying said multiple discrete supply voltage levels;

wherein said power supply is configured to provide programmable output within the dual-V_dd FPGA.

17. An FPGA as recited in claim 4, wherein said multiple discrete supply voltage levels are pre-defined for the logic blocks and routing logic within said FPGA.

18. An FPGA as recited in claim 4, further comprising:

power switches coupled between at least a portion of said logic block or said programmable routing channels and at least two of said multiple discrete supply voltage levels, and controlled by configuration bits for said FPGA;

wherein said multiple V_dd levels are selected for the logic blocks and routing logic within said FPGA at the time of programming the FPGA.

19. An FPGA as recited in claim 4, further comprising memory cells configured for controlling the selection of voltage levels used within at least portions of said integrated circuit.

20. An FPGA as recited in claim 4, wherein said logic blocks are configured with look-up tables containing memory adapted for loading with binary values that are to be output in response to a given input condition.

21. An FPGA as recited in claim 4, wherein at least a portion of the transistors in said FPGA are configured with scaled voltage threshold levels V_t.

22. An FPGA as recited in claim 21, wherein the transistors of the memory cells are configured with higher threshold voltages than the logic blocks of the FPGA, and said transistors output configuration signals through buffering to configure the operation of said logic blocks.

23. An FPGA as recited in claim 21, wherein said voltage threshold levels V_t are scaled in response to the selection of a V_dd level from multiple V_dd levels.

24. An FPGA as recited in claim 23, wherein said voltage threshold level V_t is scaled in response to the selection of a V_dd level from multiple V_dd levels to maintain a constant leakage power across all V_dd levels.

25. An FPGA as recited in claim 4, wherein said logic blocks comprise power control blocks (P-blocks) configured along with low voltage logic blocks (L-blocks) and/or high voltage logic blocks (H-blocks) which are arranged in a desired pattern.

26. An FPGA as recited in claim 25, wherein said P-blocks and H-blocks are configured in a fixed ratio toward optimizing the performance to a desired range of application.

27. An FPGA as recited in claim 25, wherein the pattern of L-blocks, P-blocks and H-blocks follows an interleaved layout pattern with a constituent repeating row pattern.

28. An FPGA as recited in claim 25, wherein L-blocks, P-blocks and H-blocks are contained within said FPGA according to a fixed ratio of approximately 1/1/2.

29. A method of placing and routing application logic within an FPGA fabric having multiple supply voltage levels, V_ddx, levels, comprising:

(a) receiving a net list;

(b) assigning critical circuit paths defined within said net list to high supply voltage levels within the FPGA;

(c) determining timing slack on non-critical circuit paths defined in said net list;

(d) determining power sensitivity of circuit non-critical circuit paths;

(e) assigning circuit paths with high power sensitivity and sufficient timing slack to logic blocks operating at a low supply voltage level;

(f) updating timing information;

(g) reversing assignment to logic blocks operating at a low supply voltage level if delay constraints are not met; and

(h) continuing, iteratively, to execute steps (e) through (g) until all circuit paths within said net list have been assigned to blocks and routes within said FPGA.

30. A method as recited in claim 29, further comprising preventing low V_dd referenced signals from driving high V_dd referenced signals.

31. A method as recited in claim 29, further comprising determining output voltages to be generated on said FPGA by a power supply configured for generating at least one of said multiple supply voltage levels toward optimizing the power-performance tradeoff.

32. A method as recited in claim 29, further comprising power gating of unused logic blocks or interconnect switches to reduce power consumption.

33. A method as recited in claim 29, further comprising coupling lowest available supply voltage level to unused logic blocks or interconnect switches to reduce power.

34. A method as recited in claim 29, further comprising using a trace-based model which collects trace information from cycle-accurate simulations of placed and routed circuits for evaluating power tradeoffs when assigning circuit paths.

35. A method as recited in claim 34, wherein the trace is reused for evaluating different V_dd and V_t combinations without the need to reroute the circuits.

36. A method as recited in claim 35, wherein the trace is reused for evaluating other device parameters selected from the set of parameters consisting essentially of Tox, size, body bias, without the need to reroute the circuits.

37. A method as recited in claim 34, further comprising performing simultaneous device and FPGA architecture evaluation within said trace-based model.

38. A method as recited in claim 29, further comprising utilizing different V_dd and V_t combinations toward reducing device power dissipation.