High Speed Level Shift Circuit with Reduced Skew and Method for Level Shifting
First Claim
1. A level shift circuit, comprising:
- a feedback transistor coupled for receiving a feedback pulse to activate the feedback transistor, and as a consequence, reduce a fall delay associated with the level shift circuit; and
a pulse generator coupled to the feedback transistor and configured for generating the feedback pulse only when an input signal and an output signal of the level shift circuit are both logic low.
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Accused Products
Abstract
An improved level shift circuit and method for level shifting is disclosed herein. In general, the improved level shift circuit adds a pulse generator, a feedback transistor and a latch to a conventional cross-coupled level shift circuit configuration. The pulse generator and feedback transistor are configured for reducing a fall delay associated with the level shift circuit. For example, the pulse generator is coupled for supplying a short duration feedback pulse to the feedback transistor during a first time period when input and output signals of the level shift circuit transition to a LOW state. The feedback pulse reduces the fall delay by increasing the speed with which the output signal is pulled LOW. The latch is coupled for preventing the feedback signal from floating when at least one of the input and output signals is HIGH. An integrated circuit comprising at least one level shift circuit is also contemplated herein.
20 Citations
22 Claims
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1. A level shift circuit, comprising:
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a feedback transistor coupled for receiving a feedback pulse to activate the feedback transistor, and as a consequence, reduce a fall delay associated with the level shift circuit; and
a pulse generator coupled to the feedback transistor and configured for generating the feedback pulse only when an input signal and an output signal of the level shift circuit are both logic low. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A method for level shifting, the method comprising:
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supplying an input signal to a level shift circuit, wherein the input signal transitions from a logic high state to a logic low state during a first time period;
generating an output signal within the level shift circuit, wherein the output signal transitions from the logic high state to the logic low state in response to the input signal supplied during the first time period; and
generating a short duration pulse within the level shift circuit to increase a speed with which the output signal transitions from the logic high state to the logic low state. - View Dependent Claims (13, 14, 15, 16)
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17. An integrated circuit comprising:
an interface circuit configured for converting a first signal level into a second signal level, which is substantially different from the first signal level, wherein the interface circuit includes at least one level shift circuit comprising;
a pair of pull-down transistors, at least one of which is coupled for receiving an input signal at the first signal level;
a pair of pull-up transistors, each coupled in series with a different one of the pair of pull-down transistors between a first power supply and ground;
an output node arranged between one of the serially-coupled pull-up and pull-down transistors for generating an output signal at the second signal level;
a feedback transistor coupled for reducing a fall delay associated with the level shift circuit by receiving a short duration pulse, which is adapted to deactivate one of the pull-up transistors faster; and
a pulse generator coupled to the feedback transistor and configured for generating the short duration pulse only when the input signal and the output signal are both logic low. - View Dependent Claims (18, 19, 20, 21, 22)
Specification