SEU hardened latches and memory cells using progrmmable resistance devices

• US 20070165446A1
• Filed: 11/02/2006
• Published: 07/19/2007
• Est. Priority Date: 11/03/2005
• Status: Active Grant

• Current Assignee: Agate Logic, Inc.
• Original Assignee: Cswitch Corporation (CloudChip, Inc.)
• Inventors: Chan, Vei-Han, Oliva, Antonietta
• Granted Patent: US 7,746,682 B2
• Time in Patent Office: Days
• US Class Current: 365/154
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: G11C 11/4125 Cells incorporating circuit means for protecting against loss of information
• CPC Class Codes: G11C 13/0002 using resistive RAM [RRAM] elements
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/025 using fullerenes, e.g. C60, or nanotubes, e.g. carbon or silicon nanotubes
• CPC Class Codes: G11C 14/009 and the nonvolatile element is a resistive RAM element, i.e. programmable resistors, e.g. formed of phase change or chalcogenide material
• CPC Class Codes: G11C 5/005 Circuit means for protection against loss of information of semiconductor storage devices

Abstract

Apparatus and methods for reducing single-event upsets (SEUs) in latch-based circuitry (e.g., static random access memory (SRAM) cells) and other digital circuitry. According to an exemplary embodiment, a latch-based circuit includes a radiation-hardened latch having first and second cross-coupled inverters and first and second programmable resistance devices (PRDs). The first PRD is coupled between the output of the first inverter and the input of the second inverter. The second PRD is coupled between the output of the second inverter and the input of the first inverter. The PRDs may be programmed to low or high-resistance states. When SET to a low-resistance state, the latch of the latch-based circuitry may be accessed to read the current logic state stored by the latch or to write a new logic state into the latch. When RESET to a high-resistance state, the latch is in a radiation-hard state, thereby preventing the latch from generating SEUs.

Claims

1. A radiation-hard latch-based circuit, comprising:

a first inverter;

a second inverter;

a first programmable resistance device (PRD) coupled between an output of the first inverter and an input of the second inverter; and

a second PRD coupled between an output of the second inverter and an input of the first inverter.

2. The radiation-hard latch-based circuit of claim 1 wherein said first and second PRDs comprise first and second phase changed devices (PCDs).

3. The radiation-hard latch-based circuit of claim 2 wherein said first and second PCDs comprise two-terminal PCDs.

4. The radiation-hard latch-based circuit of claim 2 wherein said first and second PCDs comprise a PCD having three or more terminals.

5. The radiation-hard latch-based circuit of claim 1 wherein said first and second PRDs comprise first and second programmable metallization cells (PMCs).

6. The radiation-hard latch-based circuit of claim 1 wherein said first and second PRDs comprise non-volatile devices.

7. A radiation-hard digital circuit, comprising:

means for storing a digital logic state;

at least on programmable resistance device (PRD) coupled to said means for storing a digital logic state operable to prevent said means for storing a digital logic state from changing a stored logic state depending on a programmed resistance value of said at least one PRD.

8. The radiation-hard digital circuit of claim 7 wherein said means for storing a digital logic state comprises a latch circuit.

9. The radiation-hard digital circuit of claim 7 wherein said means for storing a digital logic state comprises a static random access memory (SRAM) cell.

10. The radiation-hard-digital circuit of claim 7 wherein said at least one PRD comprises at least one phase change device (PCD).

11. The radiation-hard-digital circuit of claim 10 wherein said at least one PCD comprises at least one two-terminal PCD.

12. The radiation-hard-digital circuit of claim 10 wherein said at least one PCD comprises a PCD having three or more terminals.

13. The radiation-hard-digital circuit of claim 7 wherein said at least one PRD comprises at least one programmable metallization cell (PMC).

14. The radiation-hard digital circuit of claim 7 wherein said at least one PRD comprises a non-volatile device.

15. A method of hardening a single event upset (SEU) susceptible logic circuit from radiation, comprising:

applying a power source to at least one programmable resistance device (PRD) that is electrically coupled to at least one circuit element configured to store, or configured to participate in the storage of, a logic state;

controlling said power source to cause said at least one PRD to change from a low-resistance state to a high-resistance state; and

removing said power source to leave said at least one PRD in a non-volatile, programmed high-resistance state.

16. The method of claim 15 wherein said at least one PRD comprises at least one phase change device (PCD).

17. The method of claim 16 wherein said at least one PCD comprises a two-terminal PCD.

18. The method of claim 16 said at least one PCD comprises at least one PCD having three or more terminals.

19. The method of claim 15 wherein said at least one PRD comprises at least one programmable metallization cell (PMC).

20. The method of claim 15 wherein said at least one circuit element comprises a latch-based circuit.

21. The method of claim 15 wherein said at least one circuit element comprises a memory cell.

22. The method of claim 21 wherein said at least one memory cell comprises at least one static random access memory (SRAM) cell.

23. The method of claim 15 wherein said at least one circuit element comprise at least one transistor.