Nonvolatile memory system

• US 20070165457A1
• Filed: 12/14/2006
• Published: 07/19/2007
• Est. Priority Date: 09/30/2005
• Status: Abandoned Application

• Current Assignee: MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management)
• Original Assignee: MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management)
• Inventors: Kim, Jin-Ki
• Application Number:
  US11/639,375
• Publication Number:
  US 20070165457A1
• Time in Patent Office: Days
• US Class Current: 365/185.110
• CPC Class Codes: G06F 13/1684 using multiple buses
• CPC Class Codes: G06F 13/4234 being a memory bus
• CPC Class Codes: G06F 13/4247 on a daisy chain bus
• CPC Class Codes: G11C 16/06 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48145 the bodies being stacked
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/85399 Material
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/10253 Silicon [Si]
• CPC Class Codes: H01L 2924/12041 LED
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 Encapsulation
• CPC Class Codes: H01L 2924/19041 : being a capacitor

Abstract

A Flash memory system is implemented in a system-in-package (SIP) enclosure, the system comprising a Flash memory controller and a plurality Flash memory devices. An SIP relates to a single package or module comprising a number of integrated circuits (chips). The Flash memory controller is configured to interface with an external system and a plurality of memory devices within the SIP. The memory devices are configured in a daisy chain cascade arrangement, controlled by the Flash memory controller through commands transmitted through the daisy chain cascade.

Claims

1. A nonvolatile memory system comprising:

a plurality of nonvolatile memory devices in a daisy chain cascade arrangement; and

a nonvolatile memory controller device that interfaces with an external system and controls operations of each of the plurality of nonvolatile memory devices by communications through the daisy chain cascade arrangement.

2. The system of claim 1, wherein the plurality of memory devices are configured in a unidirectional daisy chain cascade.

3. The system of claim 2, wherein the unidirectional cascade includes a first signal path to carry signals relating to the control operations, and a second signal path to carry signals generated by the plurality of nonvolatile memory devices responsive to the control operations.

4. The system of claim 1, wherein the plurality of nonvolatile memory devices are configured in a bidirectional daisy chain cascade.

5. The system of claim 4, wherein the bidirectional cascade includes a plurality of links, each of the links configured to carry signals in two directions through the cascade.

6. The system of claim 1, wherein at least one signal path carries signals in a serial configuration through the daisy chain cascade arrangement.

7. The system of claim 6, wherein the at least one signal path includes a signal path that carries command, data and address signals.

8. The system of claim 1, wherein the plurality of nonvolatile memory devices include Flash memory that is controlled by the memory controller device.

9. The system of claim 1, wherein the memory controller device includes an external system interface and a nonvolatile memory interface, the external system interface configured for communication with an external system and the memory interface coupled to at least one of the plurality of memory devices.

10. The system of claim 1, wherein the memory controller device further comprises nonvolatile memory.

11. The system of claim 1, wherein each of the plurality of nonvolatile memory devices and the memory controller device are implemented in a common support assembly.

12. The system of claim 11, wherein each of the plurality of nonvolatile memory devices and the memory controller device are implemented in separate chips enclosed in a system-in-package (SIP) enclosure.

13. The system of claim 11, wherein the plurality of nonvolatile memory devices and the memory controller device are implemented in separate chips coupled to a circuit board.

14. The system of claim 1, wherein the controller device addresses one of the plurality of memory devices by sending an address through the daisy chain cascade, the plurality of memory devices comparing the address to a device identifier (ID) stored at each of the plurality of devices.

15. The system of claim 14, wherein each of the plurality of memory devices generates a device ID in response to communications between the memory controller device and the plurality of memory devices.

16. The system of claim 14, wherein the memory controller device sends the commands through the daisy chain cascade arrangement with the address, the address corresponding to the device ID of one of the plurality of memory devices.

17. The system of claim 1, wherein the plurality of nonvolatile memory devices include NAND Flash memory, and the nonvolatile memory controller interfaces with the external system through a NOR interface.

18. The system of claim 1, wherein the nonvolatile memory controller comprises control logic to provide mapping of logical addresses to physical addresses.

19. The system of claim 18, wherein the control logic is configured to provide wear-leveling.

20. A method of controlling a nonvolatile memory system, the method comprising:

receiving communications from an external system to a nonvolatile memory controller device;

sending a command associated with the communications from the nonvolatile memory controller device to a plurality of nonvolatile memory devices in a daisy chain cascade arrangement; and

receiving, at the nonvolatile memory controller, data from one of the plurality of nonvolatile memory devices responsive to the command.

21. The method of claim 20, wherein the plurality of memory devices are configured in a unidirectional daisy chain cascade.

22. The method of claim 20, wherein the plurality of memory devices are configured in a bi-directional daisy chain cascade.

23. The system of claim 20, further comprising sending the command in a serial configuration through the daisy chain cascade arrangement.

24. The system of claim 23, wherein the command is carried by a signal path carrying at least one of data and address signals.

25. The method of claim 20, wherein the plurality of nonvolatile memory devices include Flash memory that is controlled by the memory controller device.

26. The method of claim 20, wherein the memory controller device includes an external system interface and a nonvolatile memory interface, the external system interface configured for communication with an external system and the memory interface coupled to at least one of the plurality of memory devices.

27. The method of claim 20, wherein the memory controller device further comprises a nonvolatile memory.

28. The method of claim 20, wherein each of the plurality of nonvolatile memory devices and the memory controller device are implemented in separate chips enclosed in a system-in-package (SIP) enclosure.

29. The method of claim 20, wherein the plurality of nonvolatile memory devices and the memory controller device are implemented in separate chips coupled to a circuit board.

30. The method of claim 20, further comprising addressing one of the plurality of memory devices by sending an address through the daisy chain cascade, the plurality of memory devices comparing the address to a device identifier (ID) stored at each of the plurality of devices.

31. The method of claim 30, further comprising generating a device ID at each of the plurality of memory devices in response to communication with at least one of the memory controller device and another one of the plurality of memory devices.

32. The method of claim 30, further comprising sending the commands through the daisy chain cascade arrangement with the address, the address corresponding to the device ID of one of the plurality of memory devices.

33. A nonvolatile memory system comprising:

controlling means for controlling a plurality of nonvolatile memory devices responsive to communication with an external system; and

a plurality of nonvolatile storing means for storing data responsive to commands received from the controlling means, the plurality of nonvolatile memory devices configured in a daisy chain cascade arrangement.

34. A non-volatile memory controller comprising:

an interface to communicate with an external system; and

a processor configured to (i) receive communications from an external system; and

(ii) send a command associated with the communications to a plurality of nonvolatile memory devices in a daisy chain cascade arrangement.

35. The non-volatile memory controller of claim 34, further comprising memory containing a mapping of logical addresses to physical address in the memory devices

36. A non-volatile memory controller of claim 35 wherein the processor is further configured to provide wear leveling among the plurality of memory devices.

37. A non-volatile memory controller of claim 34, further comprising non-volatile memory connected to the plurality of nonvolatile memory devices in the daisy chain cascade arrangement.

38. The non-volatile memory controller of claim 34, wherein the processor sends, with the command, an address associated with the one of the plurality of nonvolatile memory devices.

39. The non-volatile memory controller of claim 34, wherein the processor is further configured to (iii) receive data from one of the plurality of nonvolatile memory devices responsive to the command.

40. The non-volatile memory controller of claim 34, wherein the interface is one of a NOR interface, MMC interface, SD interface, ATA interface, USB interface, and IEEE 1394 interface