Disabling faulty flash memory dies

• US 20070165461A1
• Filed: 01/18/2006
• Published: 07/19/2007
• Est. Priority Date: 01/18/2006
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Cornwell, Michael, Dudte, Christopher
• Granted Patent: US 7,609,561 B2
• Time in Patent Office: Days
• US Class Current: 365/185.330
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 29/83 with reduced power consumption
• CPC Class Codes: G11C 29/88 with partially good memories
• CPC Class Codes: G11C 29/883 using a single defective memory device with reduced capacity, e.g. half capacity
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Articles and associated methods and systems relate to disabling defective flash memory dies in a device containing multiple flash memory dies. Packages containing multiple flash memory dies may be labeled to indicate a flash memory data storage capacity based on the flash memory dies that are not disabled. Various disabling methods may be applied at the die level, package level, and/or board level.

Claims

1. A method of operating a flash memory device having multiple flash memory dies, the method comprising:

identifying one or more defective flash memory dies in a flash memory device; and

disabling memory access operations to each identified die.

2. The method of claim 1, wherein disabling memory access comprises disabling a chip enable signal to each identified die.

3. The method of claim 2, wherein disabling a chip enable signal to each identified die comprises an operation selected from the group consisting of:

disconnecting a bond wire, skipping installation of a bond wire for the chip enable signal, shorting out a signal used to generate a chip enable signal, disconnecting a chip enable pin on a package of the flash memory device, and providing an incomplete signal path for a chip enable signal.

4. The method of claim 1, wherein disabling memory access comprises disabling access to electrical power from the identified die.

5. The method of claim 4, wherein disabling access to electrical power from the identified die comprises an operation selected from the group consisting of:

disconnecting a bond wire to supply power to the identified die, skipping installation of a bond wire to supply power to the identified die, laser fusing a power connection that supplies operating power to the identified die, blowing a fuse associated with the identified die, and providing an incomplete signal path for power to the identified die.

6. The method of claim 1, wherein disabling memory access comprises configuring a memory controller to disable access to the identified die.

7. The method of claim 6, wherein configuring a memory controller to disable access to the identified die comprises configuring a memory controller in the flash device to disallow requests to read from the identified die.

8. The method of claim 6, wherein configuring a memory controller to disable access to the identified die comprises configuring a memory controller in the flash device to disallow requests to write to the identified die.

9. The method of claim 6, wherein the configured memory controller is in the identified die.

10. The method of claim 1, further comprising storing an identifier to indicate information about available flash memory capacity based on the capacity of the dies in the flash memory device other than identified die.

11. The method of claim 10, wherein the identifier is stored in the flash memory device.

12. The method of claim 1, further comprising labeling the flash memory device to indicate an amount of available flash memory in the flash memory device other than the identified die.

13. The method of claim 12, further comprising offering the flash memory device for sale.

14. A flash memory device having multiple flash memory dies, the device comprising:

one or more non-defective flash memory dies;

one or more flash memory die that have been identified as defective; and

means for disabling access to the die identified as defective.

15. The flash memory device of claim 14, wherein the access disabling means comprises means for disabling a chip enable signal to the identified die.

16. The flash memory device of claim 14, wherein the access disabling means comprises means for disabling access to electrical power from the identified die.

17. The flash memory device of claim 14, wherein the access disabling means comprises means for rejecting requests to access to the identified die.

18. The flash memory device of claim 14, further comprising a label on the flash memory device to indicate a storage capacity of the non-defective flash memory.

19. An article of manufacture comprising machine-readable instructions that, when executed, cause operations to be performed, the operations comprising:

identifying at least one criterion for determining whether a flash memory die is defective;

identifying one or more defective flash memory dies in a set of flash memory dies that provide a nominal initial capacity; and

disabling the at least one defective flash memory die to provide a flash memory system having an operational capacity that is less than the nominal initial capacity.

20. The article of claim 19, the operations further comprising assembling the flash memory system into a flash memory package.

21. The article of claim 19, wherein the operational capacity is substantially equal to the nominal initial capacity reduced by the capacity of each of the disabled dies.

22. The article of claim 21, the operations further comprising associating the operational capacity with the flash memory package.

23. The article of claim 21, the operations further comprising labeling the flash memory package with the associated operational capacity.

24. The article of claim 19, wherein identifying one or more defective flash memory dies comprises testing a flash memory package to identify at least one defective flash memory die based on the at least one criterion.

25. The article of claim 19, wherein disabling the at least one defective flash memory die comprises an operation selected from the group consisting of:

disconnecting a bond wire to supply power to the identified die;

skipping installation of a bond wire to supply power to the identified die;

laser fusing a power connection that supplies operating power to the identified die;

blowing a fuse associated with the identified die; and

, providing an incomplete signal path for power to the identified die.