Circuit for enabling sense amplifier and semiconductor memory device having the same
First Claim
1. A circuit for enabling a sense amplifier in a semiconductor memory device, the circuit comprising:
- a delay unit receiving a sense amplifier enable signal for outputting a sense amplifier enable delay signal after delaying the sense amplifier enable signal in response to a delay control signal; and
a delay control unit for controlling intensity of the delay control signal fed to the delay unit by receiving a reference signal having a temperature reduction dependent characteristic.
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Accused Products
Abstract
A circuit for enabling a sense amplifier in a semiconductor memory device includes a delay unit for outputting the delayed sense amplifier enable signal as a sense amplifier enable delay signal after delaying a sense amplifier enable signal in response to a delay control signal; and a delay control unit for controlling an intensity of the delay control signal by receiving a reference signal having a temperature reduction dependent characteristic. The length of the sensing time can increase by adjusting the delay at the sense amplifier enable signal according to a temperature decrease when a memory cell is formed on a silicon on insulator, and the sense amplifier enabling circuit is formed on a bulk silicon layer. In addition, the enable time point in the sense amplifier can be smoothly adjusted, and the possibility of operation failure in the semiconductor memory device can be reduced by reducing the occurrence of the sensing failure at the sense amplifier.
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Citations
20 Claims
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1. A circuit for enabling a sense amplifier in a semiconductor memory device, the circuit comprising:
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a delay unit receiving a sense amplifier enable signal for outputting a sense amplifier enable delay signal after delaying the sense amplifier enable signal in response to a delay control signal; and a delay control unit for controlling intensity of the delay control signal fed to the delay unit by receiving a reference signal having a temperature reduction dependent characteristic. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A circuit for enabling a sense amplifier in a semiconductor memory device, the circuit comprising:
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a delay unit for receiving a sense amplifier enable signal for outputting a sense amplifier enable delay signal after delaying the sense amplifier enable signal in response to a delay control signal; a reference signal generating unit for generating a reference signal having a temperature reduction dependent characteristic; and a delay control unit for controlling an intensity of the delay control signal fed to the delay unit by receiving the reference signal. - View Dependent Claims (14, 15, 16, 17, 18)
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19. A semiconductor memory device of a stack type, comprising:
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a sense amplifier for sensing and amplifying data on a bit line; and a sense amplifier enabling circuit for generating a sense amplifier enable delay signal for enabling the sense amplifier by receiving a reference signal having a temperature reduction dependent characteristic. - View Dependent Claims (20)
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Specification