Circuit for enabling sense amplifier and semiconductor memory device having the same

• US 20070165474A1
• Filed: 08/07/2006
• Published: 07/19/2007
• Est. Priority Date: 01/17/2006
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Park, Chul-Sung, Kim, Soo-Hwan
• Granted Patent: US 7,379,355 B2
• Time in Patent Office: Days
• US Class Current: 365/208
• CPC Class Codes: G11C 11/4091 Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
• CPC Class Codes: G11C 11/413 Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
• CPC Class Codes: G11C 2211/4016 Memory devices with silicon-on-insulator cells
• CPC Class Codes: G11C 7/02 with means for avoiding parasitic signals
• CPC Class Codes: G11C 7/08 Control thereof

Abstract

A circuit for enabling a sense amplifier in a semiconductor memory device includes a delay unit for outputting the delayed sense amplifier enable signal as a sense amplifier enable delay signal after delaying a sense amplifier enable signal in response to a delay control signal; and a delay control unit for controlling an intensity of the delay control signal by receiving a reference signal having a temperature reduction dependent characteristic. The length of the sensing time can increase by adjusting the delay at the sense amplifier enable signal according to a temperature decrease when a memory cell is formed on a silicon on insulator, and the sense amplifier enabling circuit is formed on a bulk silicon layer. In addition, the enable time point in the sense amplifier can be smoothly adjusted, and the possibility of operation failure in the semiconductor memory device can be reduced by reducing the occurrence of the sensing failure at the sense amplifier.

Claims

1. A circuit for enabling a sense amplifier in a semiconductor memory device, the circuit comprising:

a delay unit receiving a sense amplifier enable signal for outputting a sense amplifier enable delay signal after delaying the sense amplifier enable signal in response to a delay control signal; and

a delay control unit for controlling intensity of the delay control signal fed to the delay unit by receiving a reference signal having a temperature reduction dependent characteristic.

2. The circuit according to claim 1, wherein the semiconductor memory device is a stack type semiconductor memory device.

3. The circuit according to claim 1, wherein the temperature reduction dependent characteristic is a characteristic that a voltage level of the reference signal decreases as a temperature decreases.

4. The circuit according to claim 1, wherein the delay unit comprises:

a PMOS transistor connected between a first power voltage terminal and an output terminal of the delay unit, and having a gate receiving the sense amplifier enable signal; and

at least one unit inverter connected between the output terminal of the delay unit and the delay control unit and including an NMOS transistor sharing the gate of the PMOS transistor.

5. The circuit according to claim 4, wherein the delay control unit is connected between a source of the NMOS transistor in the at least one unit inverter and ground and includes a control transistor having a gate receiving a reference signal.

6. The circuit according to claim 5, wherein the control transistor is an NMOS transistor.

7. The circuit according to claim 1, further comprising a reference signal generating unit for generating the reference signal fed to the delay control unit.

8. The circuit according to claim 7, wherein the reference signal generating unit comprises:

a default voltage setting unit for providing the reference signal to an output terminal of the reference signal generating unit when an external power voltage is greater than a first power voltage;

a reference signal adjusting unit for adjusting the reference signal in consideration of a delay element caused by a process change; and

a low voltage setting unit for providing the reference signal having a certain level to the output terminal of the reference signal generating unit when the external power voltage is smaller than the first power voltage.

9. The circuit according to claim 8, wherein the default voltage setting unit comprises:

a first PMOS transistor connected between a first power voltage terminal and the output terminal of the reference signal generating unit; and

at least one NMOS transistor connected in series between the output terminal of the reference signal generating unit and ground and having a common gate receiving the first power voltage.

10. The circuit according to claim 9, wherein the reference signal adjusting unit comprises a voltage distributing circuit controlled by a bypass signal dependent on a result of a testing delay caused by a process change, and enabling a second power voltage to be distributed and applied to a substrate of the first PMOS transistor.

11. The circuit according to claim 8, wherein the low voltage setting unit comprises:

a second PMOS transistor connected between the first power voltage terminal and the output terminal of the reference signal generating unit; and

a comparator for comparing a first input signal to a second input signal and outputting a signal to the gate of the second PMOS transistor in order to turn the second PMOS transistor on or off.

12. The circuit according to claim 11, wherein the comparator outputs a signal for turning the second PMOS transistor on when the external power voltage is smaller than the first power voltage, and outputs a signal for turning the second PMOS transistor off when the external power voltage is greater than the first power voltage.

13. A circuit for enabling a sense amplifier in a semiconductor memory device, the circuit comprising:

a delay unit for receiving a sense amplifier enable signal for outputting a sense amplifier enable delay signal after delaying the sense amplifier enable signal in response to a delay control signal;

a reference signal generating unit for generating a reference signal having a temperature reduction dependent characteristic; and

a delay control unit for controlling an intensity of the delay control signal fed to the delay unit by receiving the reference signal.

14. The circuit according to claim 13, wherein the reference signal generating unit comprises:

a default voltage setting unit for providing the reference signal to an output terminal of the reference signal generating unit when an external power voltage is greater than a first power voltage;

a reference signal adjusting unit for adjusting the reference signal in consideration of a delay element caused by a process change; and

a low voltage setting unit for providing a reference signal having a certain level to the output terminal of the reference signal generating unit when the external power voltage is smaller than the first power voltage.

15. The circuit according to claim 14, wherein the delay control unit comprises at least one control transistor connected between a source of an NMOS transistor in the delay unit and ground and having a gate receiving the reference signal.

16. The circuit according to claim 14, wherein the default voltage setting unit comprises:

a first PMOS transistor connected between a first power voltage terminal and the output terminal of the reference signal generating unit; and

at least one NMOS transistor connected in series between the output terminal of the reference signal generating unit and ground and having a common gate receiving the first power voltage.

17. The circuit according to claim 16, wherein the reference signal adjusting unit comprises a voltage distributing circuit controlled by a bypass signal dependent on a result of testing delay caused by process change, and enabling an external power voltage to be distributed and applied to a substrate of the first PMOS transistor.

18. The circuit according to claim 17, wherein the low voltage setting unit comprises:

a second PMOS transistor connected between the first power voltage terminal and the output terminal of the reference signal generating unit; and

a comparator for comparing a first input signal to a second input signal and outputting a signal to the gate of the second PMOS transistor in order to turn the second PMOS transistor on or off.

19. A semiconductor memory device of a stack type, comprising:

a sense amplifier for sensing and amplifying data on a bit line; and

a sense amplifier enabling circuit for generating a sense amplifier enable delay signal for enabling the sense amplifier by receiving a reference signal having a temperature reduction dependent characteristic.

20. The device according to claim 19, wherein the sense amplifier enabling circuit comprises:

a delay unit receiving a sense amplifier enable signal for outputting a sense amplifier enable delay signal after delaying the sense amplifier enable signal in response to a delay control signal;

a reference signal generating unit for generating the reference signal; and

a delay control unit for controlling an intensity of the delay control signal by receiving the reference signal.