TRI-STATE OUTPUT DRIVER ARRANGING METHOD AND MEMORY DEVICE USING THE SAME

• US 20070165475A1
• Filed: 12/06/2006
• Published: 07/19/2007
• Est. Priority Date: 01/13/2006
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: JEONG, Woo-Pyo, CHOI, Seouk-Kyu
• Granted Patent: US 7,532,538 B2
• Time in Patent Office: Days
• US Class Current: 365/208
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1057 Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/1069 I/O lines read out arrangements

Abstract

A memory device includes a first sensing amplifier to amplify data received from the memory array, a first driver to generate a first tri-state signal responsive to the amplified data from an first sense amplifier and to provide the first tri-state signal to a data bus line, a second sensing amplifier to amplify data received from the memory array, and a second driver to generate a second tri-state signal responsive to the amplified data from an second sense amplifier and to provide the second tri-state signal to the data bus line, where the first sensing amplifier and the first driver are located in different regions of the device, and the second sensing amplifier and the second driver are located in a common region of the device.

Claims

1. A device comprising:

a first sensing amplifier to amplify data received from the memory array;

a first driver to generate a first tri-state signal responsive to the amplified data from an first sensing amplifier and to provide the first tri-state signal to a data bus line;

a second sensing amplifier to amplify data received from the memory array; and

a second driver to generate a second tri-state signal responsive to the amplified data from an second sensing amplifier and to provide the second tri-state signal to the data bus line, where the first sensing amplifier and the first driver are located in different regions of the device, and the second sensing amplifier and the second driver are located in a common region of the device.

2. The device of claim 1 where the first driver and the second driver provide a substantially equal output load to the data bus line.

3. The device of claim 1 where the data bus line receives the first tri-state signal from the first driver and the second tri-state signal from the second driver at a substantially common location on the data bus line.

6. The device of claim 1 where the second driver includes

a first transistor configured to output a supply voltage to the data bus line responsive to a first output signal from the second sensing amplifier;

and

a second transistor configured to output a ground voltage to the data bus line responsive to a second output signal from the second sensing amplifier.

7. The device of claim 6 where the second sensing amplifier includes

a NAND gate to generate the first output signal responsive to a control signal and a first data signal from the memory array;

a first inverter to invert the first data signal from the memory array;

a second NAND gate to generate an internal signal by performing a NAND operation on the control signal and a inverted first data signal; and

a second inverter to generate the second output signal by inverting the internal signal.

4. The device of claim I where the first driver includes

a first transistor configured to output a supply voltage to the data bus line responsive to a first output signal from the first sensing amplifier;

and

a second transistor configured to output a ground voltage to the data bus line responsive to a second output signal from the first sensing amplifier.

5. The device of claim 4 wherein the first sensing amplifier includes

a NAND gate to generate the first output signal responsive to a control signal and a first data signal from the memory array;

a first inverter to invert the first data signal from the memory array;

a second NAND gate to generate an internal signal by performing a NAND operation on the control signal and a inverted first data signal; and

a second inverter to generate the second output signal by inverting the internal signal.

8. A device comprising:

a plurality of input units to generate driver input signals responsive to data received from a memory array; and

a plurality of drivers, each to generate a tri-state signal responsive to respective driver input signals from associated input units, the drivers to load an output line with the tri-state signals, each tri-state signal providing a substantially equal output load to the output line.

9. The device of claim 8 including

a first input unit to generate one or more driver input signals responsive to a first data signal;

a first driver to provide a first tri-state output to the output line in response to the signals from the first input unit, where the first input unit and the first driver are located in separate regions of the device;

a second input unit to generate one or more driver input signals responsive to a second data signal; and

a second driver to provide a second tri-state output to the output line in response to the signals from the second input unit, where the second input unit and the second driver are located in the same region of the device.

10. The device of claim 9 where the first driver provides a first tri-state signal to the output line with a load that is substantially the same as a load associated with the second tri-buffer signal from the second driver.

11. The device of claim 9 where the output line receives the first tri-state signal from the first driver and the second tri-state signal from the second driver at a substantially common location on the output line.

12. A method comprising:

arranging a first sensing amplifier and a first driver of a first input/output line sensing amplifier in separate regions of a memory device, the first driver to load a data bus line with a first tri-state output; and

arranging a second sensing amplifier and a second driver of a second input/output line sensing amplifier in a common region of the memory device, the second driver to load the data bus line with a second tri-state output, where the second tri-state output loads the data bus line substantially the same as the first tri-state output.

13. The method of claim 12 where the data bus line receives the first tri-state signal from the first driver and the second tri-state signal from the second driver at a substantially common location on the data bus line.

14. A method comprising:

providing driver input signals to a plurality of drivers responsive to data signals from a memory array;

generating tri-state output signals responsive to the driver input signals; and

loading a data bus line with the tri-state output signals, each tri-state output signal loading the data bus line with a substantially equal output load.

15. The method of claim 14 includes

configuring a first input unit and a first driver in separate regions of a memory device;

configuring a second input unit and a second driver in a common region of the memory device; and

loading the data bus line with the tri-state output signals from the first and second drivers.

16. The method of claim 15 where the data bus line receives a first tri-state signal from the first driver and a second tri-state signal from the second driver at a substantially common location on the data bus line.