Fabricating method for thin film transistor array substrate and thin film transistor array substrate using the same

• US 20070166894A1
• Filed: 12/11/2006
• Published: 07/19/2007
• Est. Priority Date: 12/29/2005
• Status: Active Grant

• Current Assignee: LG Display Co., Ltd.
• Original Assignee: LG Display Co., Ltd.
• Inventors: Lim, Byoung Ho
• Granted Patent: US 7,651,899 B2
• Time in Patent Office: Days
• US Class Current: 438/151
• CPC Class Codes: G02F 1/134363 for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
• CPC Class Codes: G02F 1/13458 Terminal pads
• CPC Class Codes: G02F 1/136227 Through-hole connection of the pixel electrode to the active element through an insulation layer
• CPC Class Codes: G02F 1/136236 using a grey or half tone lithographic process
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/78633 with a light shield

Abstract

A method of fabricating a thin film transistor array substrate and a thin film transistor array substrate using the same is disclosed. Picture quality deterioration may be prevented.

Claims

1. A method of fabricating a thin film transistor array substrate, comprising:

sequentially disposing a transparent conductive material and a metal material on a substrate;

patterning with a first mask process the transparent conductive material and the metal material to provide a gate metal pattern including a gate line having a double layer structure including the transparent conductive material and the metal material, a gate electrode of a thin film transistor connected to the gate line, a gate pad extending from the gate line, a common line substantially parallel to the gate line and a common electrode substantially vertical-extended from the common line and formed in a substantially finger structure, and forming a pixel electrode made from the transparent conductive material and providing a horizontal electric field along with the common electrode;

sequentially disposing a first insulating material, a first semiconductor material and a second semiconductor material on a substrate provided with the gate metal pattern and the pixel electrode;

patterning with a second mask process the first insulating material, the first semiconductor material and the second semiconductor material to provide a gate insulating film having a first contact hole exposing the pixel electrode, an active layer made from the first semiconductor material on the gate insulating film overlapping with a gate electrode, and an ohmic contact layer made from the second semiconductor material on the active layer;

disposing a source/drain metal material on a substrate provided with the first contact hole, the active layer and the ohmic contact layer;

pattering with a third mask process the source/drain metal material to provide a data metal pattern including a gate line crossing a data line and having the gate insulating film therebetween, a drain electrode contacted, via the first contact hole, with the pixel electrode, a source electrode separated from the drain electrode with a channel of a thin film transistor therebetween and a data pad extending from the data line;

entirely coating a second insulating material on a lower substrate provided with the data metal pattern; and

patterning with a fourth mask process the second insulating material to provide a second contact hole for exposing the gate pad and a third contact hole for exposing the data pad.

2. The method of fabricating the thin film transistor array substrate as claimed in claim 1, wherein said first mask is a half-transmitting mask in which a shielding portion is formed at an area corresponding to the gate metal pattern and a half-transmitting portion is formed at an area corresponding to the pixel electrode.

3. The method of fabricating the thin film transistor array substrate as claimed in claim 1, wherein said second mask is a half-transmitting mask in which a shielding portion is formed at an area corresponding to the active layer and the ohmic contact layer, and a half-transmitting portion is formed at an area corresponding to an area of gate insulating film other than an area provided with the active layer, the ohmic contact layer and the first contact hole.

4. The method of fabricating the thin film transistor array substrate as claimed in claim 1, wherein said active layer is formed within the same area as the area where the gate electrode is formed or at a substantially narrower area than an area where the gate electrode is formed.

5. The method of fabricating the thin film transistor array substrate as claimed in claim 1, wherein said third mask process further includes the step of removing an ohmic contact layer provided at the channel portion of the thin film transistor.

6. The method of fabricating the thin film transistor array substrate as claimed in claim 1, wherein said fourth mask process further includes the step of removing a first insulating material provided at the third contact hole.

7. A thin film transistor array substrate, comprising:

a gate line having a double layer structure including a transparent conductive layer and a metal layer disposed on a substrate;

a data line crossing a gate line with a gate insulating film therebetween;

a common electrode containing a common line substantially parallel to the gate line and having a double layer structure of the transparent conductive layer and the metal layer, and having a substantially finger portion substantially vertically-extended from the common line into a pixel area defined by an intersection of the gate line and the data line;

a pixel electrode having a substantially finger portion which provides a horizontal electric field along with the common electrode at the pixel area, and made from the transparent conductive layer;

a thin film transistor having a gate electrode connected to the gate line, a source electrode connected to the data line, a drain electrode separated from the source electrode with a channel of the thin film transistor therebetween and connected, via a first contact hole for exposing the pixel electrode, to the pixel electrode, and an active layer of a substantially island-shape for forming the channel of the thin film transistor and provided on the gate insulating film at an area overlapping the gate electrode; and

a protective film for covering the data line, the source electrode and the drain electrode.

8. The thin film transistor array substrate as claimed in claim 7, wherein said active layer is formed at the same area where the gate electrode is formed or at an area substantially narrower than an area where the gate electrode is formed.

9. The thin film transistor array substrate as claimed in claim 7, further includes:

an ohmic contact layer for making ohmic contact with the source electrode and the drain electrode on the active layer of a substantially island-shape.

10. The thin film transistor array substrate as claimed in claim 9, wherein said ohmic contact layer is removed at a channel of the thin film transistor.

11. The thin film transistor array substrate as claimed in claim 7, further includes:

a gate pad extending from the gate line; and

a data pad extending from the data line.

12. The thin film transistor array substrate as claimed in claim 11, further includes:

a second contact hole passing through the gate insulating film and the protective film to expose the gate pad; and

a third contact hole passing through the protective film to expose the data pad.

13. A method of fabricating a thin film transistor array substrate, comprising:

patterning with a first mask process a transparent conductive material and a metal material to provide a gate metal pattern, a common line substantially parallel to the gate line and a common electrode substantially vertically-extended from the common line, and forming a pixel electrode made from the transparent conductive material wherein the first mask is a half-transmitting mask;

sequentially disposing a first insulating material, a first semiconductor material and a second semiconductor material on a substrate provided with the gate metal pattern and the pixel electrode;

patterning with a second mask process the first insulating material, the first semiconductor material and the second semiconductor material, an active layer made from the first semiconductor material, and an ohmic contact layer made from the second semiconductor material on the active layer wherein the second mask is a half transmitting mask;

disposing a source/drain metal material on a substrate provide with the active layer and the ohmic contact layer;

pattering with a third mask process the source/drain metal material to provide a data metal pattern;

entirely coating a second insulating material on a lower substrate provided with the data metal pattern; and

patterning with a fourth mask process the second insulating material.

14. The method of fabricating the thin film transistor array substrate as claimed in claim 13, wherein said first mask includes a shielding portion disposed at an area corresponding to the gate patterns and wherein a half-transmitting portion is positioned at an area corresponding to the pixel electrode, and a transmitting portion is positioned at a different area.

15. The method of fabricating the thin film transistor array substrate as claimed in claim 13, wherein said second mask includes a shielding portion disposed at an area corresponding to the active layer and the ohmic contact layer and wherein a transmitting portion is positioned at an area corresponding to a first contact hole for exposing the pixel electrode, and a half-transmitting portion is positioned at a different area.