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Fabricating method for thin film transistor array substrate and thin film transistor array substrate using the same

  • US 20070166894A1
  • Filed: 12/11/2006
  • Published: 07/19/2007
  • Est. Priority Date: 12/29/2005
  • Status: Active Grant
First Claim
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1. A method of fabricating a thin film transistor array substrate, comprising:

  • sequentially disposing a transparent conductive material and a metal material on a substrate;

    patterning with a first mask process the transparent conductive material and the metal material to provide a gate metal pattern including a gate line having a double layer structure including the transparent conductive material and the metal material, a gate electrode of a thin film transistor connected to the gate line, a gate pad extending from the gate line, a common line substantially parallel to the gate line and a common electrode substantially vertical-extended from the common line and formed in a substantially finger structure, and forming a pixel electrode made from the transparent conductive material and providing a horizontal electric field along with the common electrode;

    sequentially disposing a first insulating material, a first semiconductor material and a second semiconductor material on a substrate provided with the gate metal pattern and the pixel electrode;

    patterning with a second mask process the first insulating material, the first semiconductor material and the second semiconductor material to provide a gate insulating film having a first contact hole exposing the pixel electrode, an active layer made from the first semiconductor material on the gate insulating film overlapping with a gate electrode, and an ohmic contact layer made from the second semiconductor material on the active layer;

    disposing a source/drain metal material on a substrate provided with the first contact hole, the active layer and the ohmic contact layer;

    pattering with a third mask process the source/drain metal material to provide a data metal pattern including a gate line crossing a data line and having the gate insulating film therebetween, a drain electrode contacted, via the first contact hole, with the pixel electrode, a source electrode separated from the drain electrode with a channel of a thin film transistor therebetween and a data pad extending from the data line;

    entirely coating a second insulating material on a lower substrate provided with the data metal pattern; and

    patterning with a fourth mask process the second insulating material to provide a second contact hole for exposing the gate pad and a third contact hole for exposing the data pad.

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