Method to control the gate sidewall profile by graded material composition

• US 20070166902A1
• Filed: 01/13/2006
• Published: 07/19/2007
• Est. Priority Date: 01/13/2006
• Status: Active Grant

• Current Assignee: North Star Innovations Inc. (Wi-LAN Inc.)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Orlowski, Marius, Adetutu, Olubunmi, Stout, Philllip
• Granted Patent: US 7,811,891 B2
• Time in Patent Office: Days
• US Class Current: 438/197
• CPC Class Codes: H01L 21/28114 characterised by the sectional shape, e.g. T, inverted-T
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618

Abstract

A semiconductor process and apparatus uses a predetermined sequence of patterning and etching steps to etch a gate stack (30, 32) formed over a substrate (36), thereby forming an etched gate (33) having a vertical sidewall profile (35). By constructing the gate stack (30, 32) with a graded material composition of silicon-based layers, the composition of which is selected to counteract the etching tendencies of the predetermined sequence of patterning and etching steps, a more idealized vertical gate sidewall profile (35) may be obtained.

Claims

1. An integrated circuit transistor comprising:

a source;

a drain; and

a gate electrode formed from a conductive layer and having a top region, a bottom region, and first and second opposite vertical side walls, the first and second vertical side walls have a stepped surface such that a first lateral distance between the first and second vertical side walls in the top region is greater than a second lateral distance between the first and second vertical side walls in the bottom region.

2. The integrated circuit transistor of claim 1 wherein the source extends laterally under the gate, and beyond a vertical plane defined by the first vertical wall surface at the top region.

3. The integrated circuit transistor of claim 2 wherein the source is implanted in a substrate such that it does not extend laterally under the gate, beyond a vertical plane defined by the first vertical wall surface at the top region.

4. The integrated circuit transistor of claim 3 wherein the source is thermally processed, after being implanted, to laterally diffuse the source under the gate, and beyond a vertical plane defined by the first vertical wall surface at the top region.

5. The integrated circuit transistor of claim 1 wherein the drain extends laterally under the gate, and beyond a vertical plane defined by the second vertical wall surface at the top region.

6. The integrated circuit transistor of claim 5 wherein the drain is implanted in a substrate such that it does not extend laterally under the gate, beyond a vertical plane defined by the second vertical wall surface at the top region.

7. The integrated circuit transistor of claim 6 wherein the drain is thermally processed, after being implanted, to laterally diffuse the drain under the gate, and beyond a vertical plane defined by the second vertical wall surface at the top region.

8. The integrated circuit transistor of claim 1 wherein the gate electrode is formed from the single layer using a bulk etch process and a selective etch process.

9. The integrated circuit transistor of claim 1 wherein the first lateral distance is greater than the second lateral distance by approximately 20 nano meters.

10. An integrated circuit transistor gate electrode comprising:

a single layer of conductive material, the gate electrode has a top region, a bottom region, and first and second opposite vertical side walls, the first and second vertical side walls have a stepped surface such that a first lateral distance between the first and second vertical side walls in the top region is greater than a second lateral distance between the first and second vertical side walls in the bottom region.

11. The integrated circuit transistor gate electrode of claim 10 wherein the gate electrode is formed from the single layer using a bulk etch process and a selective etch process.

12. The integrated circuit transistor of claim 10 wherein the first lateral distance is greater than the second lateral distance by approximately 20 nano meters.

13. A method of fabricating an integrated circuit transistor, the method comprising:

fabricating a layer of conductive material;

performing a first etch of the conductive material to define first and second opposite vertical side walls of a gate electrode; and

performing a second etch of the conductive material to form recess regions in the first and second opposite vertical side walls, the recess regions are located at a bottom of the first and second opposite vertical side walls so that a cross-section of the gate electrode generally approximates a T-shape.

14. The method of claim 13 further comprising:

implanting source and drain regions in a substrate which is located below the layer of conductive material, a top of the gate electrode defining lateral boundaries of the source and drain regions so that the source and drain regions are not implanted under the gate electrode.

15. The method of claim 14 further comprising:

thermally processing the source and drain regions to laterally diffuse the source and drain regions under the recess regions of the gate electrode.

16. The method of claim 15 wherein the first etch removes the conductive material to expose a layer of underlaying oxide.

17. The method of claim 15 further comprises performing a third etch to remove residual conductive material remaining after the second etch.

18. The method of claim 13 wherein the recess regions have a lateral depth in the range of 5 to 20 nano meters.

19. A method of reducing overlap capacitance in an integrated circuit transistor, the method comprising:

forming a transistor gate electrode from a single layer of conductive material using an etching process, the gate electrode having a T-shaped cross section;

implanting source and drain regions in a substrate which is located below the gate electrode, a top of the gate electrode defining lateral boundaries of the source and drain regions so that the source and drain regions are not implanted under the gate electrode; and

thermally processing the implanted source and drain regions to laterally diffuse the source and drain regions under the recess regions of the gate electrode.

20. The method of claim 19 wherein the gate electrode has a bottom cross section width that is approximately 20 nano meters less than a top cross section width.

21. The method of claim 19 wherein the transistor gate electrode is formed using a bulk etch process followed by a selective etch process to form bottom side wall notches in the transistor gate electrode.

22. The method of claim 19 wherein the single layer of conductive material is polysilicon.