Three-dimensional control-gate architecture for single poly EPROM memory devices fabricated in planar CMOS technology
First Claim
1. A three dimensional capacitor structure comprising:
- a semiconductor substrate having one or more transistors fabricated therein, each having a gate with a width greater than or equal to a first line width;
a continuous diffusion region located at an upper surface of the semiconductor substrate;
a capacitor dielectric layer located on the continuous diffusion region at the upper surface of the semiconductor substrate; and
a patterned polysilicon structure located on the capacitor dielectric layer over the continuous diffusion region, the patterned polysilicon structure including one or more narrow polysilicon lines, each having a width less than the first line width.
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Accused Products
Abstract
A capacitor for a single-poly floating gate device is fabricated on a semiconductor substrate along with low and high voltage transistors. Each transistor has a gate width greater than or equal to a minimum gate width of the associated process. A dielectric layer is formed over the substrate, and a patterned polysilicon structure is formed over the dielectric layer. The patterned polysilicon structure includes one or more narrow polysilicon lines, each having a width less than the minimum gate width. The LDD implants for low and high voltage transistors of the same conductivity type are allowed to enter the substrate, using the patterned polysilicon structure as a mask. A thermal drive-in cycle results in a continuous diffusion region that merges under the narrow polysilicon lines. Contacts formed adjacent to the narrow polysilicon lines and a metal-1 trace connected to the contacts may increase the resulting capacitance.
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Citations
23 Claims
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1. A three dimensional capacitor structure comprising:
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a semiconductor substrate having one or more transistors fabricated therein, each having a gate with a width greater than or equal to a first line width;
a continuous diffusion region located at an upper surface of the semiconductor substrate;
a capacitor dielectric layer located on the continuous diffusion region at the upper surface of the semiconductor substrate; and
a patterned polysilicon structure located on the capacitor dielectric layer over the continuous diffusion region, the patterned polysilicon structure including one or more narrow polysilicon lines, each having a width less than the first line width. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A three dimensional capacitor structure comprising:
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a semiconductor substrate having one or more transistors fabricated therein, each having a gate with a width greater than or equal to a first line width;
a shallow trench isolation region located in the semiconductor substrate; and
a patterned polysilicon structure located on the shallow trench isolation region, the patterned polysilicon structure including one or more narrow polysilicon lines, each having a width less than the first line width. - View Dependent Claims (12, 13, 14, 15, 16)
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17. A method comprising:
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forming one or more transistors in a semiconductor substrate, wherein each of the one or more transistors has a gate with a width equal to or greater than a first width;
forming a capacitor dielectric layer over a first region of the semiconductor substrate;
forming a patterned polysilicon structure over the capacitor dielectric layer, wherein the patterned polysilicon structure includes one or more narrow polysilicon lines having a width less than the first width; and
thenimplanting impurities into the first region of the semiconductor substrate using the patterned polysilicon structure as a mask;
performing a thermal-drive in cycle, wherein the implanted impurities in the first region of the semiconductor diffuse to create a continuous diffusion region under the patterned polysilicon structure. - View Dependent Claims (18, 19, 20, 21, 22, 23)
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Specification