Three-dimensional control-gate architecture for single poly EPROM memory devices fabricated in planar CMOS technology

• US 20070166912A1
• Filed: 01/04/2006
• Published: 07/19/2007
• Est. Priority Date: 01/04/2006
• Status: Active Grant

• Current Assignee: Tower Semiconductor Limited
• Original Assignee: Tower Semiconductor Limited
• Inventors: Fenigstein, Amos, Roizin, Yakov, Naot, Ira, Kuritsky, Zohar, Lahav, Asaf
• Granted Patent: US 7,671,396 B2
• Time in Patent Office: Days
• US Class Current: 438/238
• CPC Class Codes: G11C 16/0408 comprising cells containing floating gate transistors G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 2216/10 Floating gate memory cells with a single polysilicon layer
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/94 Metal-insulator-semiconductors, e.g. MOS
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 41/60 the control gate being a doped region, e.g. single-poly memory cell

Abstract

A capacitor for a single-poly floating gate device is fabricated on a semiconductor substrate along with low and high voltage transistors. Each transistor has a gate width greater than or equal to a minimum gate width of the associated process. A dielectric layer is formed over the substrate, and a patterned polysilicon structure is formed over the dielectric layer. The patterned polysilicon structure includes one or more narrow polysilicon lines, each having a width less than the minimum gate width. The LDD implants for low and high voltage transistors of the same conductivity type are allowed to enter the substrate, using the patterned polysilicon structure as a mask. A thermal drive-in cycle results in a continuous diffusion region that merges under the narrow polysilicon lines. Contacts formed adjacent to the narrow polysilicon lines and a metal-1 trace connected to the contacts may increase the resulting capacitance.

Claims

1. A three dimensional capacitor structure comprising:

a semiconductor substrate having one or more transistors fabricated therein, each having a gate with a width greater than or equal to a first line width;

a continuous diffusion region located at an upper surface of the semiconductor substrate;

a capacitor dielectric layer located on the continuous diffusion region at the upper surface of the semiconductor substrate; and

a patterned polysilicon structure located on the capacitor dielectric layer over the continuous diffusion region, the patterned polysilicon structure including one or more narrow polysilicon lines, each having a width less than the first line width.

2. The three dimensional capacitor structure of claim 1, wherein the one or more narrow polysilicon lines define one or more openings in the patterned polysilicon structure.

3. The three dimensional capacitor structure of claim 2, further comprising:

pre-metal dielectric material located over the patterned polysilicon structure; and

a first set of one or more contacts extending through the pre-metal dielectric material and the one or more openings in the patterned polysilicon structure, wherein the first set of one or more contacts do not physically contact the patterned polysilicon structure.

4. The three dimensional capacitor structure of claim 3, further comprising a conductive trace located on the pre-metal dielectric material, wherein the conductive trace is in contact with the first set of one or more contacts.

5. The three dimensional capacitor structure of claim 3, further comprising a second set of one or more contacts extending through the pre-metal dielectric material adjacent to the patterned polysilicon structure.

6. The three dimensional capacitor structure of claim 3, wherein the contacts are in electrical contact with the continuous diffusion region.

7. The three dimensional capacitor structure of claim 6, further comprising at least one salicide region located on the continuous diffusion region at the upper surface of the semiconductor substrate, wherein the one of the contacts is contact with the at least one salicide region.

8. The three dimensional capacitor structure of claim 3, wherein the one or more narrow polysilicon lines include a plurality of flat surfaces and the first set of one or more contacts include a plurality of flat surfaces, wherein the flat surfaces of the one or more narrow polysilicon lines are adjacent and parallel to corresponding flat surfaces of the first set of one or more contacts.

9. The three dimensional capacitor structure of claim 1, wherein the patterned polysilicon structure further comprises an extension region having a width greater than or equal to the first line width.

10. The three dimensional capacitor structure of claim 9, wherein the extension region of the patterned polysilicon structure forms a floating gate of a non-volatile memory cell.

11. A three dimensional capacitor structure comprising:

a semiconductor substrate having one or more transistors fabricated therein, each having a gate with a width greater than or equal to a first line width;

a shallow trench isolation region located in the semiconductor substrate; and

a patterned polysilicon structure located on the shallow trench isolation region, the patterned polysilicon structure including one or more narrow polysilicon lines, each having a width less than the first line width.

12. The three dimensional capacitor structure of claim 11, further comprising:

pre-metal dielectric material located over the patterned polysilicon structure; and

a first set of one or more contacts extending through the pre-metal dielectric material adjacent to the patterned polysilicon structure, wherein the first set of one or more contacts do not physically contact the patterned polysilicon structure.

13. The three dimensional capacitor structure of claim 12, further comprising a conductive trace located on the pre-metal dielectric material, wherein the conductive trace is in contact with the first set of one or more contacts.

14. The three dimensional capacitor structure of claim 12, wherein the one or more narrow polysilicon lines include a plurality of flat surfaces and the first set of one or more contacts include a plurality of flat surfaces, wherein the flat surfaces of the one or more narrow polysilicon lines are adjacent and parallel to corresponding flat surfaces of the first set of one or more contacts.

15. The three dimensional capacitor structure of claim 11, wherein the patterned polysilicon structure further comprises an extension region having a width greater than or equal to the first line width.

16. The three dimensional capacitor structure of claim 15, wherein the extension region of the patterned polysilicon structure forms a floating gate of a non-volatile memory cell.

17. A method comprising:

forming one or more transistors in a semiconductor substrate, wherein each of the one or more transistors has a gate with a width equal to or greater than a first width;

forming a capacitor dielectric layer over a first region of the semiconductor substrate;

forming a patterned polysilicon structure over the capacitor dielectric layer, wherein the patterned polysilicon structure includes one or more narrow polysilicon lines having a width less than the first width; and

then

implanting impurities into the first region of the semiconductor substrate using the patterned polysilicon structure as a mask;

performing a thermal-drive in cycle, wherein the implanted impurities in the first region of the semiconductor diffuse to create a continuous diffusion region under the patterned polysilicon structure.

18. The method of claim 17, wherein the step of forming one or more transistors comprises:

forming a first polysilicon gate having the first width over a second region of the semiconductor substrate; and

forming a second polysilicon gate having a second width, greater than the first width, over a third region of the semiconductor substrate.

19. The method of claim 18, wherein the step of implanting impurities into the first region of the semiconductor substrate further comprises:

performing a first implant wherein impurities are implanted into the first region and the second region of the semiconductor substrate, but not the third region of the semiconductor substrate;

performing a second implant wherein impurities are implanted into the first region and the third region of the semiconductor substrate, but not the second region of the semiconductor substrate.

20. The method of claim 19, wherein the impurities of the first and second implants have the same conductivity type.

21. The method of claim 17, wherein the one or more narrow polysilicon lines define one or more openings in the patterned polysilicon structure, the method further comprising:

forming a pre-metal dielectric material over the patterned polysilicon structure; and

forming a first set of one or more contacts extending through the pre-metal dielectric material and the one or more openings in the patterned polysilicon structure, wherein the first set of one or more contacts do not physically contact the patterned polysilicon structure.

22. The method of claim 21, further comprising forming a conductive trace on the pre-metal dielectric material, wherein the conductive trace contacts the first set of one or more contacts.

23. The method of claim 21, further comprising forming a non-volatile memory cell that uses the patterned polysilicon structure as a floating gate.