Method for producing electronic chips consisting of thinned silicon

• US 20070166956A1
• Filed: 11/18/2004
• Published: 07/19/2007
• Est. Priority Date: 12/12/2003
• Status: Abandoned Application

• Current Assignee: e2v semiconductors SAS
• Original Assignee: e2v semiconductors SAS
• Inventors: Blanchard, Pierre
• Application Number:
  US10/582,711
• Publication Number:
  US 20070166956A1
• Time in Patent Office: Days
• US Class Current: 438/459
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2223/54426 for alignment
• CPC Class Codes: H01L 2223/54453 for use prior to dicing
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 27/14601 Structural or functional details thereof
• CPC Class Codes: H01L 27/1464 Back illuminated imager structures
• CPC Class Codes: H01L 27/14645 Colour imagers

Abstract

The invention relates to the fabrication of color image sensors formed on a thinned silicon substrate.

The sensor is fabricated from a semiconductor wafer (10) comprising, on its front face, a thin active layer (12) of semiconductor material, and for this purpose etched layers are formed on the active layer, the wafer is bonded by its front face onto a support substrate (40), the semiconductor wafer is thinned down by its backside, then layers of material are deposited and etched on its backside thus thinned. Also provided are narrow vertical trenches (20, 22, 24, 26) that are etched into the wafer by its front face, before the bonding operation, these trenches extending into the wafer over a depth approximately equal to the residual semiconductor wafer thickness that will remain after the thinning operation, the trenches being filled with a conducting material isolated from the active layer and forming conducting vias (20′, 22′, 24′, 26′) between the front face and the backside of the thinned layer. The purpose of the trenches is to establish electrical connections between the front face and the backside of the thinned wafer. They can also serve as markers for alignment of the front-face features with those on the backside. Lastly, they can be used to electrically isolate regions of active layers from one another.

Claims

1-15. -15. (canceled)

16. A process for the fabrication of electronic chips from a semiconductor wafer comprising, on its front face, a thin active layer of semiconductor material, the process comprising steps of:

formatting of etched layers on the active layer;

bonding the wafer by its front face onto a support substrate;

thinning down of the semiconductor wafer via its backside;

the depositing and etching of layers of material on its backside thus thinned, wherein narrow vertical trenches are etched into the wafer by its front face, before the bonding operation, these trenches extending into the wafer over a depth approximately equal to the residual semiconductor wafer thickness that will remain after the thinning operation, the trenches being filled with a conducting material isolated from the active layer and forming conducting vias between the front face and the backside of the thinned layer.

17. The process as claimed in claim 16, wherein the trenches are formed before other deposition and etching steps of electrically functional layers on the front face of the semiconductor wafer.

18. The process as claimed in claim 16, wherein the trench takes the form of an alignment marker visible from the backside after thinning in order to allow alignment of the patterns for etching of the layers on the backside with respect to the patterns for etching of layers on the front face.

19. The process as claimed in claim 16, wherein the metal layer is deposited onto the backside of the wafer after thinning, this layer being connected, by conducting vias formed within at least one narrow trench, to at least one conducting layer formed, prior to bonding the wafer onto the support substrate, on the front face of the wafer.

20. The process as claimed in claim 19, wherein the metal layer is a photo-masking layer designed to prevent light impinging on photosensitive parts within an image sensor formed on the wafer.

21. The process as claimed in claim 16, wherein layers of color filters are deposited onto the backside of the wafer after bonding and thinning.

22. The process as claimed in claim 21, wherein, after deposition of the color filters, the semiconductor wafer and its support substrate are bonded onto another, transparent, substrate and the support substrate is eliminated.

24. The process according to claim 16, wherein the role of trench is to isolate laterally one portion of active layer from other portions of active layer, and notably to isolate a region of active layer situated underneath an external connection pad from the neighboring regions of active layer.

25. The process as claimed in claim 16, wherein the semiconductor wafer comprises a highly-doped silicon substrate coated with a more lightly doped epitaxial layer forming the active layer, of around 5 to 20 microns thickness, and in that the depth of the trenches is substantially equal to the thickness of the epitaxial layer.

26. A color image sensor comprising

a support substrate,

a thin silicon layer in which a matrix of photosensitive regions is formed,

etched layers on a front face of this silicon layer,

at least one metal layer and layers of color filters etched onto the other face, i.e. the backside, of the silicon layer,

narrow vertical trenches traversing the whole of the silicon layer, having their sidewalls coated with an insulating layer and that are filled with a conducting material.

27-1. The color image sensor as claimed in claim 27, comprising a series of parallel vertical trenches disposed under the same contact pad for the external connection of the image sensor and electrically connected to this pad.