METHOD FOR FABRICATING LAST LEVEL COPPER-TO-C4 CONNECTIONWITH INTERFACIAL CAP STRUCTURE
First Claim
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1. A method comprising:
- providing a semiconductor device that comprises a last level copper interconnect embedded in a last level dielectric layer;
forming an interfacial conductive cap structure that selectively covers the last level copper interconnect, wherein said interfacial conductive cap structure comprises CoWP, NiMoP, NiMoB, NiReP, NiWP, or combinations thereof;
forming a first dielectric cap layer over the interfacial conductive cap structure and the last level dielectric layer;
forming at least one additional dielectric cap layer over the first dielectric cap layer;
forming a via through the first dielectric cap layer and the at least one additional dielectric cap layer to expose the interfacial conductive cap structure;
forming at least one ball-limiting metallurgy (BLM) layer in the via over the interfacial conductive cap structure; and
forming at least one controlled-collapse chip connection (C4) over the at least one BLM layer.
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Abstract
The present invention relates to a method for fabricating a semiconductor device with a last level copper-to-C4 connection that is essentially free of aluminum. Specifically, the last level copper-to-C4 connection comprises an interfacial cap structure containing CoWP, NiMoP, NiMoB, NiReP, NiWP, and combinations thereof. Preferably, the interfacial cap structure comprises at least one CoWP layer. Such a CoWP layer can be readily formed over a last level copper interconnect by a selective electroless plating process.
92 Citations
19 Claims
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1. A method comprising:
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providing a semiconductor device that comprises a last level copper interconnect embedded in a last level dielectric layer; forming an interfacial conductive cap structure that selectively covers the last level copper interconnect, wherein said interfacial conductive cap structure comprises CoWP, NiMoP, NiMoB, NiReP, NiWP, or combinations thereof; forming a first dielectric cap layer over the interfacial conductive cap structure and the last level dielectric layer; forming at least one additional dielectric cap layer over the first dielectric cap layer; forming a via through the first dielectric cap layer and the at least one additional dielectric cap layer to expose the interfacial conductive cap structure; forming at least one ball-limiting metallurgy (BLM) layer in the via over the interfacial conductive cap structure; and forming at least one controlled-collapse chip connection (C4) over the at least one BLM layer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A method comprising:
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providing a semiconductor device that comprises a last level copper interconnect embedded in a last level dielectric layer; forming an interfacial conductive cap structure that selectively covers the last level copper interconnect; forming a first dielectric cap layer over the interfacial conductive cap structure and the last level dielectric layer; forming at least one additional dielectric cap layer over the first dielectric cap layer; selectively removing a portion of said at least one additional dielectric cap layer to expose the first dielectric cap layer; conducting in situ sputter cleaning, which selectively removes the exposed portion of the first dielectric cap layer, stopping at the at least one additional dielectric cap layer; forming at least one ball-limiting metallurgy (BLM) layer over the interfacial conductive cap structure; and forming at least one controlled-collapse chip connection (C4) over the at least one BLM layer. - View Dependent Claims (14, 15, 16, 17, 18, 19)
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Specification