Capacitive Micromachined Ultrasonic Transducer

• US 20070167811A1
• Filed: 12/19/2006
• Published: 07/19/2007
• Est. Priority Date: 09/15/2004
• Status: Active Grant

• Current Assignee: Sonetics Ultrasound, Inc.
• Original Assignee: Sonetics Ultrasound, Inc.
• Inventors: Lemmerhirt, David, Rich, Collin
• Granted Patent: US 8,309,428 B2
• Time in Patent Office: Days
• US Class Current: 600/459
• CPC Class Codes: A61B 8/00 Diagnosis using ultrasonic, sonic or infrasonic waves imaging of objects using sonar G01S15/00
• CPC Class Codes: A61B 8/4472 Wireless probes
• CPC Class Codes: B06B 1/0292 Electrostatic transducers, e.g. electret-type

Abstract

The first integrated circuit/transducer device 36 of the handheld probe includes CMOS circuits 110 and cMUT elements 112. The cMUT elements 112 function to generate an ultrasonic beam, detect an ultrasonic echo, and output electrical signals, while the CMOS circuits 110 function to perform analog or digital operations on the electrical signals generated through operation of the cMUT elements 112. The manufacturing method for the first integrated circuit/transducer device 36 of the preferred embodiment includes the steps of depositing the lower electrode S102; depositing a sacrificial layer S104; depositing a dielectric layer S106; depositing the upper electrode S108; depositing a protective layer on the upper electrode S110; and removing the sacrificial layer S112. In the preferred embodiment, the manufacturing method also includes the step of depositing a sealant layer to seal a cavity between the lower electrode and the upper electrode S114.

Claims

1. An integrated circuit/transducer device, comprising:

a substrate;

a complementary-metal-oxide-semiconductor (CMOS) circuit fabricated on the substrate; and

a capacitive micromachined ultrasonic transducer (cMUT) element fabricated on the substrate and connected to the CMOS circuit, wherein the cMUT element includes a lower electrode adapted to maintain a first electrical potential, an upper electrode adapted to maintain a second electrical potential, and a cavity the lower electrode and the upper electrode.

2. The device of claim 1, further comprising at least 256 transducer cells, wherein each transducer cell is adapted to receive a beam signal, generate an ultrasonic beam, detect an ultrasonic echo at multiple locations, and combine the ultrasonic echoes into a single multiplexed echo signal, wherein each transducer cell includes at least one cMUT element adapted to generate ultrasonic beams and at least four cMUT elements adapted to detect ultrasonic echoes.

3. The device of claim 2, wherein the cMUT element adapted to generate ultrasonic beams and the cMUT elements adapted to detect ultrasonic echoes differ by at least one characteristic from a group consisting of diaphragm diameter, thickness, tensile stress, gap spacing, control electronics, and electrode configuration.

4. The device of claim 2, wherein the cMUT elements adapted to generate ultrasonic beams are arranged in a substantially regular hexagonal tessellation.

5. The device of claim 4, wherein each cMUT element adapted to generate an ultrasonic beam is arranged in the center of the transducer cell.

6. The device of claim 1 wherein the lower electrode is metal.

7. The device of claim 1 wherein the lower electrode is polysilicon.

8. The device of claim 1, wherein the upper electrode is disposed within the dielectric layer.

9. The device of claim 8, wherein the upper electrode is disposed on the dielectric layer and adjacent the cavity.

10. The device of claim 1 further comprising a sealant layer disposed on the dielectric layer.

11. The device of claim 10 wherein the sealant layer seals the cavity.

12. The device of claim 10 wherein the sealant is oxynitride.

13. A method of producing an integrated circuit/transducer device, the method comprising the steps of:

providing a substrate;

fabricating a complementary-metal-oxide-semiconductor (CMOS) circuit on the substrate;

fabricating a capacitive micromachined ultrasonic transducer (cMUT) element on the substrate and connecting the cMUT element to the CMOS circuit, wherein the cMUT element includes the following components that consist of layers corresponding to layers within the CMOS circuit;

a lower electrode, an upper electrode, and a sacrificial layer located between the lower electrode and the upper electrode;

removing the sacrificial layer thereby defining a cavity between the lower electrode and the upper electrode; and

depositing a sealant layer thereby sealing the cavity.

14. The method of claim 13, further comprising thinning the sealant layer.