Apparatus and methods for testing memory devices
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Abstract
Each match line of a memory device such as a content addressable memory (CAM) device and a related part of a priority encoder can be separately tested. In test mode, all match lines are first reset/disabled. A write enable pulse signal enables a match line corresponding to a CAM word line at a decoded address to be gated to the priority encoder of the CAM device. The CAM memory storage location and the comparand register are each loaded with the same test entry. A search is performed for the test entry. If the enabled match line is asserted and the priority encoder outputs the address corresponding to the CAM memory storage location, the test is successful. If not there is a match line error or a defect in the priority encoder.
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Citations
54 Claims
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1-42. -42. (canceled)
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43. A content addressable memory device, comprising:
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two or more sets of content addressable memory cells, each set of memory cells being associated with and connected to a match line that provides a match signal when items of data stored in the set of memory cells match a data item stored in a comparand register of the device;
a first circuit, the first circuit adapted to enable the match line of a set of memory cells being tested and adapted to disable match lines of other sets of memory cells;
a second circuit, the second circuit adapted to store items of data matching the data item stored in the comparand register in the set of memory cells being tested; and
a third circuit, the third circuit adapted to receive output signals from the match lines and determine whether the output signals indicate that the set of memory cells being tested has items of stored data that match the data item stored in a comparand register. - View Dependent Claims (44, 45, 46)
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47. A content addressable memory device, comprising:
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means for placing the memory device in a test mode;
means for resetting all match lines of the memory device;
means for enabling output from a match line under test;
means for decoding an address of a selected memory storage location corresponding to the match line under test;
means for loading the selected memory storage location and a comparand register with a known data pattern;
means for performing a search operation, for the known data pattern in the comparand register, on the memory device;
means for outputting a result of the search operation;
means for comparing the result of the search operation with an expected result, the expected result comprising an expected match indication on the match line under test; and
means for confirming proper operation of the memory device if the result of the search operation is equal to the expected result. - View Dependent Claims (48, 49, 50, 51)
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52. A method of operating a content addressable memory device, the method comprising:
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placing the memory device in a test mode;
resetting all match lines of the memory device on the rising edge of a clock signal;
enabling a match line under test;
decoding an address of a selected memory storage location corresponding to the match line under test on the rising edge of the clock signal;
loading the selected memory storage location and a comparand register with a known data pattern on the rising edge of the clock signal;
performing a search operation for the known data pattern;
comparing a result of the search operation with an expected result of the search operation, whereby the expected result comprises an expected match line indication for the match line under test; and
if the result of the search operation does not match the expected result, the method further comprises indicating an error of the memory device, and if the result of the search operation matches the expected result, the method further comprises confirming proper operation of the memory device. - View Dependent Claims (53, 54)
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Specification