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Start/stop circuit for performance counter

  • US 20070168807A1
  • Filed: 08/23/2005
  • Published: 07/19/2007
  • Est. Priority Date: 08/23/2005
  • Status: Active Grant
First Claim
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1. A circuit for tracking a number of clock cycles between occurrences of an event of interest, the circuit comprising:

  • logic for asserting a run signal responsive to a first occurrence of the event of interest;

    logic for deasserting the run signal responsive to a second occurrence of the event of interest; and

    logic for incrementing a count value on each clock cycle while the run signal is asserted.

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