Start/stop circuit for performance counter
First Claim
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1. A circuit for tracking a number of clock cycles between occurrences of an event of interest, the circuit comprising:
- logic for asserting a run signal responsive to a first occurrence of the event of interest;
logic for deasserting the run signal responsive to a second occurrence of the event of interest; and
logic for incrementing a count value on each clock cycle while the run signal is asserted.
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Abstract
A circuit for tracking a number of clock cycles between occurrences of an event of interest is described. The circuit comprises logic for asserting a run signal responsive to a first occurrence of the event of interest; logic for deasserting the run signal responsive to a second occurrence of the event of interest; and logic for incrementing a count value on each clock cycle while the run signal is asserted.
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Citations
30 Claims
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1. A circuit for tracking a number of clock cycles between occurrences of an event of interest, the circuit comprising:
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logic for asserting a run signal responsive to a first occurrence of the event of interest;
logic for deasserting the run signal responsive to a second occurrence of the event of interest; and
logic for incrementing a count value on each clock cycle while the run signal is asserted. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A circuit for tracking a number of clock cycles between occurrences of an event of interest, the circuit comprising:
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means for asserting a run signal responsive to a first occurrence of the event of interest;
means for deasserting the run signal responsive to a second occurrence of the event of interest; and
means for incrementing a count value on each clock cycle while the run signal is asserted. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20)
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21. A method of tracking a number of clock cycles between occurrences of an event of interest, the method comprising:
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asserting a run signal responsive to a first occurrence of the event of interest;
deasserting the run signal responsive to a second occurrence of the event of interest; and
incrementing a count value on each clock cycle while the run signal is asserted. - View Dependent Claims (22, 23, 24, 25, 26, 27, 28, 29, 30)
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Specification