Method for implementing error-correction codes in flash memory

• US 20070168837A1
• Filed: 04/03/2006
• Published: 07/19/2007
• Est. Priority Date: 01/18/2006
• Status: Active Grant

• Current Assignee: Western Digital Israel Limited (Western Digital Corporation)
• Original Assignee: M-Systems Flash Disk Pioneers Ltd. (Western Digital Corporation)
• Inventors: Murin, Mark
• Granted Patent: US 7,783,955 B2
• Time in Patent Office: Days
• US Class Current: 714/763
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence

Abstract

The present invention teaches a method and device for implementing error-correction code (ECC) in flash memory. The present invention discloses methods which utilize a modified ECC algorithm, and a flash memory device which incorporates these methods.

Claims

1. A method for storing data bits into a flash memory device, the method comprising the steps of:

(a) providing an error-correction code for generating at least one parity bit from a plurality of data bits;

(b) transforming the data bits to be stored in the flash memory device, thereby generating a plurality of transformed data bits;

(c) applying said error-correction code to said plurality of transformed data bits, thereby generating at least one parity bit;

(d) transforming said at least one parity bit, thereby generating at least one transformed parity bit; and

(e) storing the data bits and said at least one transformed parity bit into the flash memory device.

2. The method of claim 1, wherein said step of applying said error-correction code to said plurality of transformed data bits does not generate an all-one codeword for any value of the data bits.

3. The method of claim 1, wherein said step of storing into the flash memory device includes storing an all-one group of bits for at least one value of the data bits.

4. The method of claim 1, wherein said step of transforming the data bits, thereby generating said plurality of transformed data bits, includes generating complements of the data bits.

5. The method of claim 1, wherein said step of transforming at least one parity bit, thereby generating at least one transformed parity bit, includes generating a complement of said at least one parity bit.

6. A flash memory device for storing data bits, the device comprising:

(a) an error-correction code module for generating parity bits from a plurality of data bits, said error-correction code module configured to generate at least one parity bit from said plurality of data bits; and

(b) a flash memory controller for;

(i) transforming data bits to be stored in the flash memory device, said flash memory controller configured to generate a plurality of transformed data bits;

(ii) transforming said at least one parity bit, said flash memory controller configured to generate at least one transformed parity bit; and

(iii) storing the data bits and said at least one transformed parity bit into the flash memory device.

7. The device of claim 6, wherein said error-correction code module is included in said flash memory controller.

8. The device of claim 6, wherein said error-correction code module is included in a host system.

9. The device of claim 6, wherein a codeword generated by said error-correction code module from said plurality of data bits is not an all-one codeword for any value of the data bits.

10. The device of claim 6, wherein said flash memory controller is configured to store an all-one group of bits for at least one value of the data bits.

11. The device of claim 6, wherein said plurality of transformed data bits is a plurality of complements of the data bits.

12. The device of claim 6, wherein said at least one transformed parity bit is a complement of said at least one parity bit.