DUAL-PROCESSOR COMPLEX DOMAIN FLOATING-POINT DSP SYSTEM ON CHIP

• US 20070168908A1
• Filed: 10/30/2006
• Published: 07/19/2007
• Est. Priority Date: 03/26/2004
• Status: Abandoned Application

• Current Assignee: Atmel Corporation (Microchip Technology Incorporated)
• Original Assignee: Atmel Corporation (Microchip Technology Incorporated)
• Inventors: Cosimi, Maurizio, Michelotti, Andrea, Bazzana, Piergiovanni, Altieri, Benedetto, Paolucci, Pier, Pastorelli, Elena, Ricciardi, Andrea, Aglietti, Federico, Cerruto, Antonio
• Application Number:
  US11/554,448
• Publication Number:
  US 20070168908A1
• Time in Patent Office: Days
• US Class Current: 717/100
• CPC Class Codes: G06F 7/483 Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers G06F7/4806, G06F7/4824, G06F7/49, G06F7/491, G06F7/544 take precedence
• CPC Class Codes: G06F 9/3879 for non-native instruction execution, e.g. executing a command; for Java instruction set
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units

Abstract

A system for digital signal processing, configured as a system on chip (SoC), combines a microprocessor core and digital signal processor (DSP) core with floating-point data processing capability. The DSP core can perform operations on floating-point data in a complex domain and is capable of producing real and imaginary arithmetic results simultaneously. This capability allows a single-cycle execution of, for example, FFT butterflies, complex domain simultaneous addition and subtraction, complex multiply accumulate (MULACC), and real domain dual multiply-accumulators (MACs). The SoC may be programmed entirely from a microprocessor programming interface, using calls from a DSP library to execute DSP functions. The cores may also be programmed separately. Capability for programming and simulating the entire SoC are provided by a separate programming environment. The SoC may have heterogeneous processing cores in which either processing core may act as master or slave, or both cores may operate simultaneously and independently.

Claims

1. A software development environment, comprising:

means for microprocessor code development; and

means for digital signal processor code development, said means for digital signal processor code development being capable of performing operations on floating-point data in a complex domain.

2. The software development environment of claim 1, wherein said means for digital signal processor code development incorporates pipelining and parallelism management.

3. The software development environment of claim 1, wherein said means for digital signal processor code development incorporates code compression.

4. The software development environment of claim 1, wherein said software development environment incorporates a cycle accurate simulator.

5. The software development environment of claim 1, wherein said software development environment incorporates an instruction accurate simulator.

6. The software development environment of claim 1, wherein said software development environment incorporates a compiler for a C programming language.

7. The software development environment of claim 1, wherein said software development environment incorporates a graphical user interface.

8. The software development environment of claim 1, wherein said microprocessor is a reduced instruction set computer (RISC) processor.

9. The software development environment of claim 1, wherein said digital signal processor utilizes a very long instruction word (VLIW) architecture.

10. A compiler for translating a source program language, including a plurality of instructions, into an object program, the compiler comprising:

translation means for translating instructions written in a syntax compliant with said source program language; and

translation means for translating a library of callable digital signal processing functions, said compiler being capable of operating on a set of extended data types.

11. The compiler of claim 10, wherein said source program language is a C++ source program written in a syntax compliant with International Organization for Standardization (ISO) C and said library of callable digital signal processing functions are C callable digital signal processing functions.

12. The compiler of claim 10, wherein said extended data types are selected from the group consisting of int, float, _complex_int, _complex_float, vector int, vector float, pointers, arrays, structures, and unions.

13. The compiler of claim 10, further comprising means for declaring variables accessing at least one or more of register memory, internal data memory, and external data memory.

14. The compiler of claim 13, further comprising means for optimizing register usage.

15. The compiler of claim 11, further comprising means for translating in-line assembly language instructions with C++ operands.

16. The compiler of claim 11, further comprising means for translating American National Standards Institute (ANSI) C standard math library functions.

17. The compiler of claim 11, further comprising:

language extensions to implement IF statement translation with entire condition expression evaluation; and

language extensions to implement WHERE statement translation.