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Reset circuit, data carrier and communication device

  • US 20070170256A1
  • Filed: 02/24/2005
  • Published: 07/26/2007
  • Est. Priority Date: 02/27/2004
  • Status: Abandoned Application
First Claim
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1. Reset circuit comprising a clock signal input for receiving a clock signal consisting of a sequence of clock signal cycles, comprising a data signal input for receiving digital data signals, said digital data signals being encoded in such a manner that at least one signal edge appears per data bit in the data signal, comprising a counting stage being connected to the data signal input and the clock signal input and being designed for counting a number of clock signal cycles, which clock signal cycles appear between a defined number of data signal edges, and comprising comparing means, said comparing means being designed for comparing the number of clock signal cycles counted by the counting stage with a lower limit and/or with an upper limit and said comparing means being designed to emit a reset signal, if the number either remains below the lower limit or exceeds the upper limit, depending on the limit value taken for comparison.

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