Reset circuit, data carrier and communication device

• US 20070170256A1
• Filed: 02/24/2005
• Published: 07/26/2007
• Est. Priority Date: 02/27/2004
• Status: Abandoned Application

• Current Assignee: NXP B.V. (NXP Semiconductors NV)
• Original Assignee: Koninklijke Philips Electronics N.V. (Koninklijke Philips N.V.)
• Inventors: Breitfuss, Klemens
• Application Number:
  US10/590,619
• Publication Number:
  US 20070170256A1
• Time in Patent Office: Days
• US Class Current: 235/451
• CPC Class Codes: H04L 25/4904 using self-synchronising codes, e.g. split-phase codes

Abstract

In a reset circuit (1) comprising a clock signal input (RC) for receiving a clock singal CL MD signal (CL) consisting of a sequence of clock signal cycles, and comprising a data signal input (RD) for receiving digital data signals (MD), which are encoded in such a manner that at least one signal edge (0→1, 1→ 0) appears per data bit in the data signal, are provided a counter (2) being connected to the data signal input (RD) and the clock signal input (RC) and being designed for counting the number (X) of clock signal cycles, which appear between a defined number of data signal edges, and comparing means (3), which comparing means (3) being designed for comparing the number (X) of clock signal cycles counted by the counter (2) with a lower limit (MIN) and/or with an upper limit (MAX) and which comparing means (3) being designed to produce a reset signal (RS), if the number (X) either remains below the lower object (MIN) or exceeds the upper limit (MAX), depending on the limit value (MIN, MAX) taken for comparison.

Claims

1. Reset circuit comprising a clock signal input for receiving a clock signal consisting of a sequence of clock signal cycles, comprising a data signal input for receiving digital data signals, said digital data signals being encoded in such a manner that at least one signal edge appears per data bit in the data signal, comprising a counting stage being connected to the data signal input and the clock signal input and being designed for counting a number of clock signal cycles, which clock signal cycles appear between a defined number of data signal edges, and comprising comparing means, said comparing means being designed for comparing the number of clock signal cycles counted by the counting stage with a lower limit and/or with an upper limit and said comparing means being designed to emit a reset signal, if the number either remains below the lower limit or exceeds the upper limit, depending on the limit value taken for comparison.

2. A data carrier comprising a logic circuit said logic circuit being designed for receiving digital data signals and for producing output data and for receiving a reset signal said reset signal being provided to set the logic circuit into a defined logical state, wherein the data carrier comprising a reset circuit as claimed in claim 1 and wherein the reset signal of the reset circuit being provided to be supplied to the logic circuit.

3. A data carrier as claimed in claim 2, wherein the data carrier comprising a pad for connecting external data input lines, data output lines, clock signal lines and preferably power supply lines to the reset circuit and the logic circuit respectively.

4. A data carrier as claimed in claim 2, wherein the data carrier comprising a coupling element for contactless transmission of signals and comprising an air interface for processing received signals, wherein the air interface being provided for extracting data signals and clock signals from the received signals and for forwarding the extracted data signals to the reset circuit and the logic circuit respectively.

5. A data carrier as claimed in claim 4, wherein the air interface being designed for extracting electrical energy for supplying the reset circuit and the logic circuit with energy, wherein the extracted electrical energy being preferably buffered intermediately in an energy storage means.

6. A data carrier as claimed in claim 2, wherein the data carrier comprising a subscriber'"'"'s identification module for a mobile telephone application.

7. A communication device comprising a data carrier as claimed in claim 2.

8. A communication device being designed for communicating with a data carrier as claimed in claim 3, wherein the communication device comprising a coupling element for contactless transmission of signals and an air interface for processing received signals, wherein the air interface being provided for extracting digital data reception signals and clock signals from the received signals and for making the digital data reception signals available for forwarding to the data carrier.

9. A communication device as claimed in claim 8, wherein the air interface comprising a pseudo data generator said data generator being designed for making a pseudo data signal, which said pseudo data signal being coded in such a way that at least one signal edge occurs per data bit in the data signal, available for forwarding to the data carrier, if no signals can be received by the coupling element from which signals valid data reception signals could be extracted.

10. A communication device as claimed in claim 8, wherein the air interface comprising a pseudo clock signal generator said pseudo clock signal generator being designed for making available a pseudo clock signal consisting of a sequence of clock signal cycles for forwarding to the data carrier, if no electromagnetic signals can be received by the coupling element from which electromagnetic signals valid clock signals could be extracted.

11. A communication device as claimed in claim 7, wherein the communication device being designed as a mobile phone, a personal digital assistant or a personal computer.

12. A reset method for resetting a data carrier and its logic circuit respectively, in a defined logical state, comprising reception of a clock signal consisting of a sequence of clock signal cycles, and comprising reception of digital data signals, said digital data signals being encoded in such a manner that at least one signal edge appears per data bit in the data signal and comprising counting of a number of clock signal cycles, which clock signal cycles appear between a defined number of data signal edges, and comprising comparison of the number of counted clock signal cycles with a lower limit and/or with an upper limit and comprising emitting of a reset signal for the logic circuit if the number either remains below the lower limit or exceeds the upper limit depending on the limit value taken for comparison.