Integrated Circuit with Embedded FeRAM-based RFID

• US 20070170267A1
• Filed: 08/30/2006
• Published: 07/26/2007
• Est. Priority Date: 09/02/2005
• Status: Active Grant

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: Kang, Hee-Bok, Ahn, Jin-Hong
• Granted Patent: US 7,883,019 B2
• Time in Patent Office: Days
• US Class Current: 235/492
• CPC Class Codes: G06K 19/07749 the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
• CPC Class Codes: G06K 19/07775 the antenna being on-chip
• CPC Class Codes: G06K 19/07779 the inductive antenna being a coil
• CPC Class Codes: H01L 2223/54433 containing identification or tracking information
• CPC Class Codes: H01L 2223/54446 Wireless electrical read out
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

An integrated circuit (IC) includes a high capacitance solid state circuit region configured to perform predetermined operations, a RFID block comprising a FeRAM block for storing data, and an interface unit configured to transfer to the RFID block an externally-provided unique ID for wirelessly identifying the IC, the unique ID being stored in the FeRAM block. The IC further includes a conductive trace extending through predetermined regions of the IC, the conductive trace being configured as an antenna for the RFID block, wherein the RFID block is configured to receive and transmit information to an external source via the antenna.

Claims

1. An integrated circuit (IC) comprising:

a high capacitance solid state circuit region configured to perform predetermined operations;

a RFID block comprising a FeRAM block for storing data;

an interface unit configured to transfer to the RFID block an externally-provided unique ID for wirelessly identifying the IC, the unique ID being stored in the FeRAM block; and

a conductive trace extending through predetermined regions of the IC, the conductive trace being configured as an antenna for the RFID block, wherein the RFID block is configured to receive and transmit information to an external source via the antenna.

2. The IC of claim 1 wherein the high capacitance solid state circuit region comprises one or more of DRAM, Flash memory, FeRAM, CPU, system on chip (SoC), and ASIC.

3. The IC of claim 1 wherein the conductive trace extends along the periphery of the IC.

4. The IC of claim 1 wherein the RFID block comprises:

an analog block having a demodulator circuit configured to demodulate RF signals received via the antenna and generate command signals corresponding to the received RF signals; and

a digital block configured to receive the command signals from the demodulator block and in response generate address and control signals coupled to the FeRAM block.

5. The IC of claim 4 wherein:

the FeRAM block is configured to receive the address and command signals from the digital block and in response provide data previously stored in the FeRAM, the provided data corresponding to the RF signals received via the antenna, and

the analog block further comprising a modulator circuit configured to modulate the data provided by the FeRAM block and generate signals to be transmitted to the external source via the antenna.

6. The IC of claim 5 wherein:

the FeRAM block is configured to receive the address and command signals from the digital block and in response provide data previously stored in the FeRAM, the provided data corresponding to the RF signals received via the antenna, and

the analog block further comprising a modulator circuit configured to modulate the data provided by the FeRAM block and generate signals to be transmitted to the external source via the antenna.

7. The IC of claim 1 wherein the RFID block comprises:

an analog block having a demodulator circuit configured to demodulate RF signals received via the antenna and generate command signals corresponding to the received RF signals; and

a digital block configured to receive the command signals from the demodulator block and in response generate address, data and control signals coupled to the FeRAM block.

8. The IC of claim 7 wherein the FeRAM block is configured to receive the address, data and command signals from the digital block and in response store the received data in memory locations corresponding to the received address.

9. The IC of claim 1 wherein the RFID block further includes a voltage multiplier circuit configured to convert RF signals received via the antenna to a supply voltage for powering the RFID block.

10. The IC of claim 9 wherein the RFID block further includes a power on reset circuit configured to detect the supply voltage and power up the RFID block when the supply voltage reaches a predetermined level.

11. The IC of claim 1 wherein the FeRAM block comprises:

a control circuit configured to receive control signals and to determine whether the control signals correspond to a read operation or a write operation;

a memory array comprising a plurality of FeRAM cells arranged along rows and columns;

a decoder coupled to the memory array and configured to select FeRAM cells in response to address signals received by the FeRAM block;

sense amplifiers coupled to the memory array and configured to sense data stored in the selected FeRAM cells in a read operation; and

I/O buffers configured to transfer data received by the FeRAM unit to the memory array in a write operation and to output the sensed data in a read operation.

12. The IC of claim 11 wherein FeRAM cells along each column are connected to a bitline, and each FeRAM cell comprises a transistor and a FeRAM capacitor serially connected between a bitline and a plate line PL, the transistors in FeRAM cells along a row having their gates coupled to a wordline.

13. The IC of claim 1 further comprising:

a built-in self-test (BIST) block configured to carry out testing of the IC when prompted to do so; and

a BIST interface unit coupled between the RFID block and the BIST unit, the BIST interface unit being configured to supply commands generated by the RFID block to the BIST block, and to transfer test results from a BIST operation to the RFID block.

14. A method for wireless exchange of information with IC dies each including a RFID block and an antenna to enable wireless communication with the IC die, the method comprising:

storing a unique identification code in each of the IC dies;

testing each IC die; and

storing at least part of the test results from the testing step in the corresponding IC die,

wherein the unique identification code stored in each IC die together with the RFID block and the antenna of each IC die enable wireless retrieval of the test results stored in each IC die.

15. The method of claim 14 wherein the unique identification code stored in each IC die together with the RFID block and the antenna of each IC die enable wireless retrieval of the test results from each IC die after each IC die is packaged.

16. The method of claim 14 wherein the unique identification code stored in each IC die together with the RFID block and the antenna of each IC die enable wireless retrieval of the test results from each IC die before each IC die is packaged.

17. The method of claim 14 wherein the testing step is carried when the IC dies are on a semiconductor wafer so that the test results correspond to wafer test.

18. The method of claim 14 wherein the testing step is carried after the IC dies are packaged so that the test results correspond to package test.

19. The method of claim 14 further comprising:

using the unique identification code for each IC die, wirelessly retrieving the test results stored in each IC die.

20. The method of claim 14 wherein the step of storing the test results comprises:

using the unique identification code for each IC die, wirelessly storing the test results in corresponding IC dies.

21. The method of claim 14 wherein each IC die includes an interface unit coupled to the RFID block, wherein the test results are stored in the RFID block of corresponding IC dies via their respective interface unit.

22. The method of claim 14 wherein each IC die comprises an interface unit coupled to the RFID block, wherein each unique identification code is stored in the RFID block of the corresponding IC die via the interface unit.

23. The method of claim 14 wherein the test results correspond to one or more of wafer test results, quality assurance test results, and package test results.

24. The method of claim 14 further comprising:

storing tracking information in each IC die, the tracking information identifying one or more of;

manufacturing plant in which the IC die is manufactured, process technology used to manufacture the IC die, wafer lot to which the IC die belongs, the location of the IC die on a wafer from which the IC die is extracted, type of package in which the IC die is housed, packaging plant in which the IC die is packaged,

wherein the unique identification code stored in each IC die together with the RFID block and the antenna of each IC die enable wireless retrieval of the tracking information stored in each IC die.

25. The method of claim 14 wherein each IC die includes one or more of DRAM, Flash memory, FeRAM, CPU, system on chip (SoC), and ASIC.

26. A method for increasing use efficiency of packaged IC dies each including a RFID block and an antenna to enable wireless communication with the IC die, the method comprising:

prior to packaging the IC dies, storing a unique identification code in each of the IC dies, wherein the unique identification code stored in each IC die together with the RFID block and the antenna of each IC die enable wireless disabling of a defective portion of a packaged IC die so that a remaining functional portion of the packaged IC die can be used.

27. The method of claim 26 further comprising:

using the unique identification code for each IC die, wirelessly disabling only the defective portion of the packaged IC die so that a remaining functional portion of the packaged IC die can be used.

28. The method of claim 26 further comprising:

using the unique identification code for each IC die, wirelessly identifying the defective portion of the packaged IC die.

29. The method of claim 26 wherein each IC die comprises an interface unit and a RFID block coupled to one another, wherein each unique identification code is stored in the RFID block of the corresponding IC die via the IC die'"'"'s interface unit.

30. The method of claim 26 wherein each IC die includes one or more of DRAM, Flash memory, FeRAM, CPU, system on chip (SoC), and ASIC.