Semiconductor device and manufacturing method thereof

• US 20070170499A1
• Filed: 01/22/2007
• Published: 07/26/2007
• Est. Priority Date: 01/23/2006
• Status: Abandoned Application

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Inventors: Araki, Noriaki
• Application Number:
  US11/655,986
• Publication Number:
  US 20070170499A1
• Time in Patent Office: Days
• US Class Current: 257/330
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66621 using etching to form a recess at the gate location etching of semiconductor bodies H01L21/302

Abstract

A semiconductor device has elements formed on a substrate separately from each other. Each of the elements includes first and second regions as a source and a drain; a gate electrode formed to have a buried gate structure, and a portion of the gate electrode is put between the first and second regions. The width of the gate electrode is wider than the gate width of the first and second regions.

Claims

1. A semiconductor device having a source and a drain, said device comprising:

first and second regions as said source and said drain, respectively; and

a gate electrode formed to have a buried gate structure, a portion of said gate electrode being put between said first and second regions,

wherein a width of said gate electrode is wider than a gate width of said first and second regions.

2. The semiconductor device according to claim 1, wherein said gate electrode has a third portion which is not put between said first and second regions, and

a gate length between said first and second regions is shorter than a length of said third portion in a gate length direction.

3. The semiconductor device according to claim 1, wherein said gate electrode has a third portion which is not put between said first and second regions, and

two ends of said third portion are provided for ends in a gate width direction.

4. The semiconductor device according to claim 1, wherein each of said first and second regions is contact with an element separation region at a part of sides other than a side opposite to a side of the other.

5. The semiconductor device according to claim 1, wherein each of said first and second regions is contact with an element separation region at a whole of sides other than a side opposite to a side of the other.

6. The semiconductor device according to claim 2, wherein said elements are arranged, and

said gate electrode is common to said elements and has said third portion length between said elements.

7. The semiconductor device according to claim 1, wherein a depth of said element separation region is substantially a same as that of said gate electrode.

8. The semiconductor device according to claim 1, wherein a depth of said element separation region is deeper than that of said gate electrode.

9. A method of manufacturing a semiconductor device, comprising:

forming a conductive region on a semiconductor substrate;

performing a first patterning to said conductive layer and said semiconductor substrate by using a first mask to form a gate electrode trench, a device separation trench, and first and second regions;

filling said gate electrode trench and said device separation trench with a gate electrode material;

forming a resist pattern by using a second mask having a pattern coarser than said first mask;

removing said gate electrode material from a part of said gate electrode trench and said device separation trench by said resist pattern; and

filing said gate electrode trench part and said device separation trench with an insulating film to form a device separation region.

10. The method of manufacturing a semiconductor device according to claim 9, wherein a width of said gate electrode is wider than a width of said first and second regions in a gate width direction.

11. The method of manufacturing a semiconductor device according to claim 9, wherein a gate length between said first and second regions is shorter than a length of a third portion of said gate electrode which is not put between said first and second regions, in a gate length direction.

12. The method of manufacturing a semiconductor device according to claim 9, wherein a depth of said device separation region is substantially a same as that of said gate electrode.

13. The method of manufacturing a semiconductor device according to claim 9, wherein a depth of said device separation region is deeper than that of said gate electrode.

14. The method of manufacturing a semiconductor device according to claim 9, further comprising:

before filling said gate electrode material into said gate electrode trench and said device separation trench, forming a gate oxide film on a bottom and side wall of said gate electrode trench and said device separation trench.

15. A method of manufacturing a semiconductor device, comprising:

forming a conductive region on a semiconductor substrate;

performing a first patterning to said conductive layer and said semiconductor substrate by using a first mask to form a gate electrode trench, a device separation trench, and first and second regions;

filling said gate electrode trench and said device separation trench with an insulating film to form a device separation region;

forming a resist pattern by using a second mask having a pattern coarser than said first mask, to expose a part of said gate electrode trench and a periphery of said gate electrode trench;

removing said insulating film from a region not covered by said resist pattern; and

filling a gate electrode material in a region from which said insulating film is removed, to form a gate electrode.

16. The method of manufacturing a semiconductor device according to claim 15, wherein a width of said gate electrode is wider than a width of said first and second regions in a gate width direction.

17. The method of manufacturing a semiconductor device according to claim 15, wherein a gate length between said first and second regions is shorter than a length of a third portion of said gate electrode which is not put between said first and second regions, in a gate length direction.

18. The method of manufacturing a semiconductor device according to claim 15, wherein a depth of said device separation region is substantially a same as that of said gate electrode.

19. The method of manufacturing a semiconductor device according to claim 15, wherein a depth of said device separation region is deeper than that of said gate electrode.

20. The method of manufacturing a semiconductor device according to claim 15, further comprising:

before filling said gate electrode material into said gate electrode trench and said device separation trench, forming a gate oxide film on a bottom and side wall of said gate electrode trench and said device separation trench.