THIN-FILM TRANSISTOR AND MANUFACTURING METHOD THEREOF

• US 20070170526A1
• Filed: 01/19/2007
• Published: 07/26/2007
• Est. Priority Date: 01/23/2006
• Status: Active Grant

• Current Assignee: NLT Technologies, Ltd. (Tianma Microelectronics Company Limited)
• Original Assignee: NEC Corporation, NEC LCD Technologies Limited (Tianma Microelectronics Company Limited)
• Inventors: SATOU, Tadashi
• Granted Patent: US 7,618,881 B2
• Time in Patent Office: Days
• US Class Current: 257/408
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/6675 Amorphous silicon or polysilicon transistors
• CPC Class Codes: H01L 29/78621 with LDD structure or an extension or an offset region or characterised by the doping profile
• CPC Class Codes: H01L 29/78648 arranged on opposing sides of the channel

Abstract

A method for forming a thin-film transistor on an insulating substrate includes the steps of: forming a non-single-crystal semiconductor thin film on the insulating substrate; forming a gate insulating film on the non-single-crystal semiconductor thin film; forming a gate electrode including a lower gate electrode and an upper gate electrode on the gate insulating film, the lower gate electrode having a portion that is not covered by the upper gate electrode; forming a source-drain region and an LDD (lightly doped drain) region in the non-single-crystal thin film semiconductor film at a time by introducing an impurity into the non-single-crystal semiconductor thin film through the gate electrode and the gate insulating film; and etching away an exposed portion of the lower gate electrode by using the upper gate electrode as a mask.

Claims

1. A thin-film transistor comprising:

a non-single-crystal semiconductor thin film formed on an insulating substrate;

a gate insulating film formed on the non-single-crystal semiconductor thin film;

a gate electrode formed on the gate insulating film and including a lower gate electrode and an upper gate electrode; and

a Lightly Doped Drain structure including a heavily doped region and a lightly doped region formed in the non-single-crystal semiconductor thin film;

wherein a difference in impurity concentration between the lightly doped region and the heavily doped region is equivalent to a concentration of an impurity blocked by the lower gate electrode from being introduced; and

the gate electrode does not exist over the lightly doped region.

2. The thin-film transistor according to claim 1, wherein the non-single-crystal semiconductor thin film is a polysilicon thin film.

3. The thin-film transistor according to claim 2, wherein the lower gate electrode is made from a microcrystalline silicon thin film and said upper gate electrode is made from a metal film.

10. A liquid-crystal display apparatus comprising:

the insulating substrate on which the thin-film transistor according to claim 1 is formed;

a counter substrate;

an liquid-crystal element sandwiched between the insulating substrate and the counter substrate; and

a driving circuit which drives the liquid-crystal element through the thin-film transistor.

4. A method for manufacturing a thin-film transistor, comprising the steps of:

forming a non-single-crystal semiconductor thin film on an insulating substrate;

forming a gate insulating film on the non-single-crystal semiconductor thin film;

forming a gate electrode including a lower gate electrode and an upper gate electrode on the gate insulating film, the lower gate electrode having a portion that is not covered by the upper gate electrode;

forming a heavily doped region and a lightly doped region in the non-single-crystal semiconductor thin film at a time by introducing an impurity into the non-single-crystal semiconductor thin film through the gate electrode and the gate insulating film; and

etching away an exposed portion of the lower gate electrode by using the upper gate electrode as a mask.

5. The method according to claim 4, wherein the step of forming a gate electrode comprises the steps of:

forming a conductive film including a plurality of layers on the gate insulating film; and

forming the gate electrode by selectively etching the conductive film.

6. The method according to claim 4, wherein the step of forming a gate electrode comprises the steps of:

forming a conductive film including a plurality of layers on the gate insulating film;

selectively forming a photoresist film on a top layer of the conductive film; and

forming the upper gate electrode by applying isotropic etching to the conductive film by using the photoresist film as a mask and forming the lower gate electrode by applying anisotropic etching to the conductive film by using the photoresist film as a mask.

7. The method according to claim 6, wherein the isotropic etching is wet etching.

8. The method according to claim 7, wherein the gate insulating film is a silicon dioxide thin film, the conductive film including the plurality of layers includes a lower, microcrystalline silicon thin film and upper, chromium thin film;

and

an etchant used in the wet etching is an aqueous solution of diammonium cerium (IV) nitrate and perchloric acid.

9. The method according to claim 4, wherein the non-single-crystal semiconductor thin film is a polysilicon thin film.