Semiconductor device having flange structure

• US 20070170556A1
• Filed: 12/07/2006
• Published: 07/26/2007
• Est. Priority Date: 01/20/2006
• Status: Abandoned Application

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Chung, Hyun-Soo, Lee, Dong-Ho, Lee, In-Young, Jang, Dong-Hyeon
• Application Number:
  US11/635,011
• Publication Number:
  US 20070170556A1
• Time in Patent Office: Days
• US Class Current: 257/666
• CPC Class Codes: H01L 2224/02166 Collar structures
• CPC Class Codes: H01L 2224/023 Redistribution layers [RDL] for bonding areas
• CPC Class Codes: H01L 2224/05001 Internal layers
• CPC Class Codes: H01L 2224/05022 the internal layer being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/05024 the internal layer being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05099 Material
• CPC Class Codes: H01L 2224/05548 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05557 comprising protrusions or indentations
• CPC Class Codes: H01L 2224/0558 being stacked
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/10126 Bump collar
• CPC Class Codes: H01L 2224/13 of an individual bump connector
• CPC Class Codes: H01L 2224/13024 the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 24/03 Manufacturing methods
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/10 Bump connectors bumps on insulating substrates, e.g. chip carriers, H01L23/49816; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/11 Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0001 : Technical content checked by a classifier
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H05K 1/111 : Pads for surface mounting, e.g. lay-out
• CPC Class Codes: H05K 2201/09745 : Recess in conductor, e.g. in pad or in metallic substrate
• CPC Class Codes: H05K 2203/1184 : Underetching, e.g. etching of substrate under conductors or etching of conductor under dielectrics; Means for allowing or controlling underetching
• CPC Class Codes: H05K 3/062 : consisting of metals or alloys or metallic inorganic compounds H05K3/065 takes precedence
• CPC Class Codes: H05K 3/3452 : Solder masks
• CPC Class Codes: H05K 3/3457 : Solder materials or compositions; Methods of application thereof
• CPC Class Codes: Y02P 70/50 : Manufacturing or production processes characterised by the final manufactured product

Abstract

A semiconductor device may include a semiconductor element. A layer of material may be provided on the semiconductor element which may have an opening through which a bond pad may be exposed. At least one flange structure may be provided on the first bond pad, the at least one flange structure made of at least two metal layers with different etch rates.

Claims

1. A semiconductor device comprising:

a semiconductor element;

a layer of material provided on the semiconductor element having an opening through which a first bond pad is exposed; and

at least one flange structure provided on the first bond pad, the at least one flange structure made of at least two metal layers with different etch rates.

2. The semiconductor device of claim 1, wherein the semiconductor element is a semiconductor chip having a passivation layer exposing a second bond pad, wherein the layer of material is a first interlayer insulating layer, the semiconductor device further comprising a bond pad redistribution pattern interposed between the passivation layer and the first interlayer insulating layer and connected to the second bond pad.

3. The semiconductor device of claim 2, wherein the at least one flange structure includes a first flange structure on an edge of the first bond pad and a second flange structure on a middle portion of the first bond pad.

4. The semiconductor device of claim 2, wherein the at least one flange structure comprises:

a lower metal layer provided on the bond pad redistribution pattern; and

an upper metal layer provided on the lower metal layer, and protruding beyond a side wall of the lower metal layer,

wherein the lower metal layer has a higher etch rate relative to the upper metal layer.

5. The semiconductor device of claim 2, wherein the at least one flange structure comprises:

a lower metal layer formed on the bond pad redistribution pattern;

a middle metal layer provided on the lower metal layer and protruding beyond a side wall of the lower metal layer; and

an upper metal layer provided on the middle metal layer and protruding beyond a side wall of the middle metal layer,

wherein the lower metal layer has a highest etch rate, the middle metal layer has an intermediate etch rate, and the upper metal layer has a lowest etch rate, relative to each of the other layers.

6. The semiconductor device of claim 4, wherein the thickness of the lower metal layer is greater than that of the upper metal layer.

7. The semiconductor device of claim 2, further comprising a seed layer interposed between the bond pad redistribution pattern and the at least one flange structure.

8. The semiconductor device of claim 2, further comprising a second interlayer insulating layer interposed between the passivation layer and the bond pad redistribution pattern.

9. The semiconductor device of claim 7, wherein the seed layer is formed of one of titanium or chrome.

10. The semiconductor device of claim 4, wherein the lower metal layer is formed of nickel and the upper metal layer is formed of gold (Au).

11. The semiconductor device of claim 1, wherein the semiconductor element is a semiconductor chip having an integrated circuit and the layer of material is a passivation layer provided on the surface of the semiconductor chip.

12. The semiconductor device of claim 11, wherein the at least one flange structure includes a first flange structure on an edge of the first bond pad and a second flange structure on a middle portion of the first bond pad.

13. The semiconductor device of claim 11, wherein the at least one flange structure comprises:

a lower metal layer provided on the first bond pad; and

an upper metal layer provided on the lower metal layer, protruding beyond a side wall of the lower metal layer,

wherein the lower metal layer has a higher etch rate relative to the upper metal layer.

14. The semiconductor device of claim 11, wherein the at least one flange structure comprises:

a lower metal layer provided on the first bond pad;

a middle metal layer provided on the lower metal layer, protruding beyond a side wall of the lower metal layer; and

an upper metal layer provided on the middle metal layer, protruding beyond a side wall of the middle metal layer,

wherein the lower metal layer has a highest etch rate, the middle metal layer has an intermediate etch rate, and the upper metal layer has a lowest etch rate, relative to each of the other layers.

15. The semiconductor device of claim 13, wherein the thickness of the lower metal layer is greater than that of the upper metal layer.

16. The semiconductor device of claim 1, wherein the semiconductor element is an insulating substrate having a printed circuit pattern provided on a surface, and the layer of material is a resist provided on the surface of the insulating substrate.

17. The semiconductor device of claim 16, wherein the insulating substrate is formed from one of polyimide, FR4 resin and BT resin.

18. The semiconductor device of claim 16, wherein the at least one flange structure includes a first flange structure on an edge of the first bond pad and a second flange structure on a middle portion of the first bond pad.

19. The semiconductor device of claim 16, wherein the at least one flange structure comprises:

a lower metal layer provided on the printed circuit pattern; and

an upper metal layer provided on the lower metal layer, protruding beyond a side wall of the lower metal layer,

wherein the lower metal layer has a higher etch rate relative to the upper metal layer.

20. The semiconductor device of claim 17, wherein the at least one flange structure comprises:

a lower metal layer provided on the first bond pad;

a middle metal layer provided on the lower metal layer, and protruding beyond a side wall of the lower metal layer; and

an upper metal layer provided on the middle metal layer, and protruding beyond a side wall of the middle metal layer,

wherein the lower metal layer has a highest etch rate, the middle metal layer has an intermediate etch rate, and the upper metal layer has a lowest etch rate, relative to each of the other layers.

21. The semiconductor device of claim 19, wherein the thickness of the lower metal layer is greater than that of the upper metal layer.

22. The semiconductor device of claim 1, wherein the at least one flange structure is a locking structure.